imx6: clock: allow different clock sources for ldb

The LDB clock sources don't have to be the same, so allow DI1 clock to
be configured separately.

Unlikely to be significant, but the reason will become apparent in the
following commit.

Signed-off-by: Brian Ruley <brian.ruley@gehealthcare.com>

diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 81af89c631f5517b017c5f4536f0bb35e7cf2afb..9c5f3090bd8c7278b88fb6257a3d6e5d8d21975c 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -82,7 +82,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
 void mxs_set_lcdclk(u32 base_addr, u32 freq);
-void select_ldb_di_clock_source(enum ldb_di_clock clk);
+void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1);
 void enable_eim_clk(unsigned char enable);
 int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
                      char *const argv[]);

diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index b5aa606b8d01c8c58c57df755741f600ea9a35f3..d366180e78826e001aef7ed6e910535cd16ee8b5 100644 (file)
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -1452,7 +1452,7 @@ static void enable_ldb_di_clock_sources(void)
  * Try call this function as early in the boot process as possible since the
  * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
  */
-void select_ldb_di_clock_source(enum ldb_di_clock clk)
+void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
        int reg;
@@ -1525,8 +1525,8 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
        reg = readl(&mxc_ccm->cs2cdr);
        reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
              | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
-       reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
-             | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+       reg |= ((clk0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+             | (clk1 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
        writel(reg, &mxc_ccm->cs2cdr);
 
        /* Unbypass pll3_sw_clk */

diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 8cfac9fbb3427ac902c540ae7e5dbae93bba19fb..4a2349e165b1481c6377b0d54f0880603e5bec81 100644 (file)
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -218,7 +218,7 @@ static void set_gpr_register(void)
 
 int board_early_init_f(void)
 {
-       select_ldb_di_clock_source(MXC_PLL5_CLK);
+       select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
        set_gpr_register();
 
        /*

diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c
index ddb7304d493ae58861942c24772ba99995710ab3..f7751fd6fb131a0a071cf4236ae012f2e9ad5af7 100644 (file)
--- a/board/ge/b1x5v2/b1x5v2.c
+++ b/board/ge/b1x5v2/b1x5v2.c
@@ -320,7 +320,7 @@ int overwrite_console(void)
 
 int board_early_init_f(void)
 {
-       select_ldb_di_clock_source(MXC_PLL5_CLK);
+       select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
 
        return 0;
 }

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index e1d08475e9492d81fdc4962b4e70fb9d25da3b86..9fc5f604a4946d76fe7c3731765453d98208ade4 100644 (file)
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -383,7 +383,7 @@ int board_early_init_f(void)
 
 #if defined(CONFIG_VIDEO_IPUV3)
        /* Set LDB clock to Video PLL */
-       select_ldb_di_clock_source(MXC_PLL5_CLK);
+       select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
 #endif
        return 0;
 }