amdgpu/jpeg: fix deepsleep register for jpeg 5_0_0 and 5_0_2

PCTL0__MMHUB_DEEPSLEEP_IB is 0x69004 on MMHUB 4,1,0 and
and 0x60804 on MMHUB 4,2,0. 0x62a04 is on MMHUB 1,8,0/1.

The DS bits are adjusted to cover more JPEG engines and MMHUB
version.

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 4b4aa95536242306f5def65a89626ee025c22aa8..82abe181c7309945bdc6486f078dfae9b266ff12 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -736,15 +736,35 @@ static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring)
  */
 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring)
 {
-       if (!amdgpu_sriov_vf(ring->adev)) {
+       struct amdgpu_device *adev = ring->adev;
+
+       if (!amdgpu_sriov_vf(adev)) {
+               int jpeg_inst = GET_INST(JPEG, ring->me);
+               uint32_t value = 0x80004000; /* default DS14 */
+
                amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
                        0, 0, PACKETJ_TYPE0));
-               amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
+
+               /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */
+               switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
+               case IP_VERSION(4, 1, 0):
+                       amdgpu_ring_write(ring, 0x69004);
+                       value = 0x80010000;
+                       break;
+               case IP_VERSION(4, 2, 0):
+                       amdgpu_ring_write(ring, 0x60804);
+                       if (jpeg_inst & 1)
+                               value = 0x80010000;
+                       break;
+               default:
+                       amdgpu_ring_write(ring, 0x62a04);
+                       break;
+               }
 
                amdgpu_ring_write(ring,
                                  PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0,
                                          0, PACKETJ_TYPE0));
-               amdgpu_ring_write(ring, 0x80004000);
+               amdgpu_ring_write(ring, value);
        }
 }
 
@@ -757,15 +777,35 @@ void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring)
  */
 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring)
 {
-       if (!amdgpu_sriov_vf(ring->adev)) {
+       struct amdgpu_device *adev = ring->adev;
+
+       if (!amdgpu_sriov_vf(adev)) {
+               int jpeg_inst = GET_INST(JPEG, ring->me);
+               uint32_t value = 0x00004000; /* default DS14 */
+
                amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
                        0, 0, PACKETJ_TYPE0));
-               amdgpu_ring_write(ring, 0x62a04);
+
+               /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */
+               switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
+               case IP_VERSION(4, 1, 0):
+                       amdgpu_ring_write(ring, 0x69004);
+                       value = 0x00010000;
+                       break;
+               case IP_VERSION(4, 2, 0):
+                       amdgpu_ring_write(ring, 0x60804);
+                       if (jpeg_inst & 1)
+                               value = 0x00010000;
+                       break;
+               default:
+                       amdgpu_ring_write(ring, 0x62a04);
+                       break;
+               }
 
                amdgpu_ring_write(ring,
                                  PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0,
                                          0, PACKETJ_TYPE0));
-               amdgpu_ring_write(ring, 0x00004000);
+               amdgpu_ring_write(ring, value);
        }
 }