* when they are not attached to an Realtek SoC. The paradigm should be to keep the PHY
* implementation bus independent.
*
- * As if this is not enough the PHY packages consist of 4 or 8 ports that all can be
- * programmed individually. Some registers are only available on port 0 and configure
- * the whole package.
- *
* To bring all this together we need a tricky bus design that intercepts select page
* calls but lets raw page accesses through. And especially knows how to handle raw
* accesses to the select register. Additionally we need the possibility to write to
int raw_page;
int bus_map_base;
int port_map_base;
- int (*read_mmd_phy)(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 *val);
- int (*read_phy)(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val);
+ int (*read_mmd_phy)(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val);
+ int (*read_phy)(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val);
int (*reset)(struct mii_bus *bus);
void (*setup_polling)(struct mii_bus *bus);
- int (*write_mmd_phy)(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 val);
- int (*write_phy)(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val);
+ int (*write_mmd_phy)(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val);
+ int (*write_phy)(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val);
};
struct rtmdio_phy_info {
RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1, RTMDIO_838X_CMD_FAIL);
}
-static int rtmdio_838x_read_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val)
+static int rtmdio_838x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
u32 park_page = 31;
int err;
- regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(port));
- regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, port << 16);
+ regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
+ regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, addr << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1,
reg << 20 | park_page << 15 | page << 3);
err = rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_READ_C22);
return err;
}
-static int rtmdio_838x_write_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val)
+static int rtmdio_838x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
u32 park_page = 31;
- regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(port));
+ regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, val << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1,
reg << 20 | park_page << 15 | page << 3);
return rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C22);
}
-static int rtmdio_838x_read_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 *val)
+static int rtmdio_838x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
int err;
- regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(port));
- regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, port << 16);
+ regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
+ regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, addr << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3, devnum << 16 | regnum);
err = rtmdio_838x_run_cmd(bus, RTMDIO_838X_CMD_READ_C45);
if (!err)
return err;
}
-static int rtmdio_838x_write_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 val)
+static int rtmdio_838x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
- regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(port));
+ regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2, val << 16);
regmap_write(ctrl->map, RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3, devnum << 16 | regnum);
RTMDIO_839X_PHYREG_ACCESS_CTRL, RTMDIO_839X_CMD_FAIL);
}
-static int rtmdio_839x_read_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val)
+static int rtmdio_839x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
int err;
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_CTRL, 0x1ff);
- regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, port << 16);
+ regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, addr << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL,
reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23);
err = rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C22);
return err;
}
-static int rtmdio_839x_write_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val)
+static int rtmdio_839x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_CTRL, 0x1ff);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val << 16);
- regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(port));
- regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(port) >> 32);
+ regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(addr));
+ regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(addr) >> 32);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_ACCESS_CTRL,
reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23);
return rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C22);
}
-static int rtmdio_839x_read_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 *val)
+static int rtmdio_839x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
int err;
- regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, port << 16);
+ regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, addr << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_MMD_CTRL, (devnum << 16) | (regnum & 0xffff));
err = rtmdio_839x_run_cmd(bus, RTMDIO_839X_CMD_READ_C45);
if (!err)
return err;
}
-static int rtmdio_839x_write_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 val)
+static int rtmdio_839x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
- regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(port));
- regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(port) >> 32);
+ regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL, BIT_ULL(addr));
+ regmap_write(ctrl->map, RTMDIO_839X_PHYREG_PORT_CTRL + 4, BIT_ULL(addr) >> 32);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_DATA_CTRL, val << 16);
regmap_write(ctrl->map, RTMDIO_839X_PHYREG_MMD_CTRL, (devnum << 16) | (regnum & 0xffff));
RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1, RTMDIO_930X_CMD_FAIL);
}
-static int rtmdio_930x_write_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val)
+static int rtmdio_930x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
u32 park_page = 31;
- regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(port));
+ regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, val << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1,
reg << 20 | page << 3 | park_page << 15);
return rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C22);
}
-static int rtmdio_930x_read_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val)
+static int rtmdio_930x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
u32 park_page = 31;
int err;
- regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, port << 16);
+ regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, addr << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1,
reg << 20 | page << 3 | park_page << 15);
err = rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_READ_C22);
return err;
}
-static int rtmdio_930x_write_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 val)
+static int rtmdio_930x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
- regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(port));
+ regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0, BIT(addr));
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, val << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3, (devnum << 16) | (regnum & 0xffff));
return rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C45);
}
-static int rtmdio_930x_read_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 *val)
+static int rtmdio_930x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
int err ;
- regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, port << 16);
+ regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2, addr << 16);
regmap_write(ctrl->map, RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3, (devnum << 16) | (regnum & 0xffff));
err = rtmdio_930x_run_cmd(bus, RTMDIO_930X_CMD_READ_C45);
if (!err)
RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0, RTMDIO_931X_CMD_FAIL);
}
-static int rtmdio_931x_write_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 val)
+static int rtmdio_931x_write_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
- u64 mask = BIT_ULL(port);
+ u64 mask = BIT_ULL(addr);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2, (u32)mask);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4, (u32)(mask >> 32));
return rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C22);
}
-static int rtmdio_931x_read_phy(struct mii_bus *bus, u32 port, u32 page, u32 reg, u32 *val)
+static int rtmdio_931x_read_phy(struct mii_bus *bus, u32 addr, u32 page, u32 reg, u32 *val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
int err;
- regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, port << 5);
+ regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, addr << 5);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0, reg << 6 | page << 11);
err = rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_READ_C22);
if (!err)
return err;
}
-static int rtmdio_931x_read_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 *val)
+static int rtmdio_931x_read_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 *val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
int err;
- regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, port << 5);
+ regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL, addr << 5);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_MMD_CTRL, (devnum << 16) | (regnum & 0xffff));
err = rtmdio_931x_run_cmd(bus, RTMDIO_931X_CMD_READ_C45);
if (!err)
return err;
}
-static int rtmdio_931x_write_mmd_phy(struct mii_bus *bus, u32 port, u32 devnum, u32 regnum, u32 val)
+static int rtmdio_931x_write_mmd_phy(struct mii_bus *bus, u32 addr, u32 devnum, u32 regnum, u32 val)
{
struct rtmdio_ctrl *ctrl = bus->priv;
- u64 mask = BIT_ULL(port);
+ u64 mask = BIT_ULL(addr);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2, (u32)mask);
regmap_write(ctrl->map, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 + 4, (u32)(mask >> 32));
phyinfo->has_res_reg = true;
break;
default:
- pr_warn("skip polling setup for unknown PHY %08x on port %d\n", phyid, addr);
+ pr_warn("skip polling setup for unknown PHY %08x on address %d\n", phyid, addr);
ret = -EINVAL;
break;
}
/*
* Control bits EX_PHY_MAN_xxx have an important effect on the detection of the media
* status (fibre/copper) of a PHY. Once activated, register MAC_LINK_MEDIA_STS can
- * give the real media status (0=copper, 1=fibre). For now assume that if port 24 is
+ * give the real media status (0=copper, 1=fibre). For now assume that if address 24 is
* PHY driven, it must be a combo PHY and media detection is needed.
*/
combo_phy = ctrl->smi_bus[24] < 0 ? 0 : BIT(7);
struct rtmdio_phy_info phyinfo;
unsigned int mask, val;
- /* reset all ports to "SerDes driven" */
+ /* set everthing to "SerDes driven" */
regmap_write(ctrl->map, RTMDIO_930X_SMI_MAC_TYPE_CTRL, 0);
/* Define PHY specific polling parameters */
if (rtmdio_get_phy_info(bus, addr, &phyinfo))
continue;
- /* set port to "PHY driven" */
+ /* set to "PHY driven" */
mask = addr > 23 ? 0x7 << ((addr - 24) * 3 + 12): 0x3 << ((addr / 4) * 2);
val = phyinfo.mac_type << (ffs(mask) - 1);
regmap_update_bits(ctrl->map, RTMDIO_930X_SMI_MAC_TYPE_CTRL, mask, val);
struct rtmdio_ctrl *ctrl = bus->priv;
u32 c45_mask = 0;
- /* Disable port polling for configuration purposes */
+ /* Disable polling for configuration purposes */
regmap_write(ctrl->map, RTMDIO_931X_SMI_PORT_POLLING_CTRL, 0);
regmap_write(ctrl->map, RTMDIO_931X_SMI_PORT_POLLING_CTRL + 4, 0);
msleep(100);
struct rtmdio_phy_info phyinfo;
u32 val;
- /* reset all ports to "SerDes driven" */
+ /* set everything to "SerDes driven" */
for (int reg = 0; reg < 4; reg++)
regmap_write(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + reg * 4,
RTMDIO_931X_SMI_PHY_ABLTY_SDS * 0x55555555U);
if (rtmdio_get_phy_info(bus, addr, &phyinfo))
continue;
- /* set port to "PHY driven" */
+ /* set to "PHY driven" */
mask = GENMASK(1, 0) << ((addr % 16) * 2);
val = RTMDIO_931X_SMY_PHY_ABLTY_MDIO << (ffs(mask) - 1);
regmap_update_bits(ctrl->map, RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + (addr / 16) * 4,
continue;
if (addr < 0 || addr >= ctrl->cfg->num_phys) {
- dev_err(dev, "illegal port number %d\n", addr);
+ dev_err(dev, "illegal address number %d\n", addr);
of_node_put(np);
return -EINVAL;
}
projects / thirdparty / openwrt.git / commitdiff
