drm/amdgpu: Fix incorrect VRAM GART mappings on non-4K page size systems

When mapping VRAM pages into the GART page table,
amdgpu_gart_map_vram_range() assumes that the system page size is the
same as the GPU page size.

On systems with non-4K page sizes, multiple GPU pages can exist within
a single CPU page. As a result, the mappings are created incorrectly
because fewer page table entries are programmed than required.

Fix this by programming the mappings correctly for non-4K page size
systems.

Fixes: 237d623ae659 ("drm/amdgpu/gart: Add helper to bind VRAM pages (v2)")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Donet Tom <donettom@linux.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit a8f0bc22388f74e0cf4ed8b7d1846c580eaf44cc)
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index b6f849d51c2e77a658fbf7b1e1d93502d26b45ac..c4c21dbbbdbf800599e6b899324a5a8d29032e05 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -394,7 +394,8 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
                                uint64_t start_page, uint64_t num_pages,
                                uint64_t flags, void *dst)
 {
-       u32 i, idx;
+       u32 i, j, t, idx;
+       u64 page_base;
 
        /* The SYSTEM flag indicates the pages aren't in VRAM. */
        WARN_ON_ONCE(flags & AMDGPU_PTE_SYSTEM);
@@ -402,9 +403,12 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
        if (!drm_dev_enter(adev_to_drm(adev), &idx))
                return;
 
-       for (i = 0; i < num_pages; ++i) {
-               amdgpu_gmc_set_pte_pde(adev, dst,
-                       start_page + i, pa + AMDGPU_GPU_PAGE_SIZE * i, flags);
+       page_base = pa;
+       for (i = 0, t = 0; i < num_pages; i++) {
+               for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
+                       amdgpu_gmc_set_pte_pde(adev, dst, start_page + t, page_base, flags);
+                       page_base += AMDGPU_GPU_PAGE_SIZE;
+               }
        }
 
        drm_dev_exit(idx);