aarch64: Remove +sme+nosve sorry

The preceding patches have fixed support for SME without SVE enabled, so
we can now remove the "sorry" for this configuration.  This allows us to
remove SVE/SVE2 from the features that are added as a workaround when
trying to process a streaming function with SME disabled.

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (aarch64_override_options_internal):
	Remove +sme+nosve sorry, and remove SVE from nosme workaround.
	* doc/invoke.texi: Remove SVE2 requirement from +sme.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/no-sve-with-sme-1.c: Removed.
	* gcc.target/aarch64/no-sve-with-sme-2.c: Removed.
	* gcc.target/aarch64/no-sve-with-sme-3.c: Removed.
	* gcc.target/aarch64/no-sve-with-sme-4.c: Removed.

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 3f1b7dfb9d306cf1f5c5aafafbd750b3aef13b10..ffef5ad29b3ab179528b3ee75859bbe93d8a8e0d 100644 (file)
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19695,10 +19695,7 @@ aarch64_override_options_internal (struct gcc_options *opts)
              " option %<-march%>, or by using the %<target%>"
              " attribute or pragma", "sme");
       opts->x_target_flags &= ~MASK_GENERAL_REGS_ONLY;
-      auto new_flags = (isa_flags
-                       | feature_deps::SME ().enable
-                       /* TODO: Remove once we support SME without SVE2.  */
-                       | feature_deps::SVE2 ().enable);
+      auto new_flags = isa_flags | feature_deps::SME ().enable;
       aarch64_set_asm_isa_flags (opts, new_flags);
     }
 
@@ -19831,12 +19828,6 @@ aarch64_override_options_internal (struct gcc_options *opts)
       & AARCH64_EXTRA_TUNE_DISPATCH_SCHED)
     gcc_assert (aarch64_tune_params.dispatch_constraints != NULL);
 
-  /* TODO: SME codegen without SVE2 is not supported, once this support is added
-     remove this 'sorry' and the implicit enablement of SVE2 in the checks for
-     streaming mode above in this function.  */
-  if (TARGET_SME && !TARGET_SVE2)
-    sorry ("no support for %qs without %qs", "sme", "sve2");
-
   /* Set scalar costing to a high value such that we always pick
      vectorization.  Increase scalar costing by 10000%.  */
   if (opts->x_flag_aarch64_max_vectorization)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 60d0b570710c9d4d6cca41e61b798a7c273c13f7..fe20ae66c00b8f7d812a56c103b5577732fc121e 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21863,8 +21863,7 @@ Enable the Common Short Sequence Compression instructions.
 Enable the shorter compare and branch instructions, @code{cbb}, @code{cbh} and
 @code{cb}.
 @item sme
-Enable the Scalable Matrix Extension.  This is only supported when SVE2 is also
-enabled.
+Enable the Scalable Matrix Extension.
 @item sme-i16i64
 Enable the FEAT_SME_I16I64 extension to SME.  This also enables SME
 instructions.

diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c
deleted file mode 100644 (file)
index e5bb2d9..0000000
--- a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* { dg-do compile } */
-/* { dg-skip-if "Do not override mcpu or march" { *-*-* } { -mcpu=* -march=* } { "" } } */
-/* { dg-options { "-march=armv8-a+sme" } } */
-/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */
-int main (void)
-{
-  return 0;
-}

diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c
deleted file mode 100644 (file)
index 13f09b3..0000000
--- a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* { dg-do compile } */
-/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */
-
-#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma")
-
-int main (void)
-{
-  return 0;
-}

diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c
deleted file mode 100644 (file)
index 9e3cbeb..0000000
--- a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* { dg-do compile } */
-/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */
-
-int __attribute__ ((target( "arch=armv8.2-a+ssve-fp8fma"))) main (void)
-{
-  return 0;
-}
-

diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c
deleted file mode 100644 (file)
index 04a33a7..0000000
--- a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* { dg-do compile } */
-/* { dg-skip-if "Do not override mcpu or march" { *-*-* } { -mcpu=* -march=* } { "" } } */
-/* { dg-options { "-march=armv8-a" } } */
-/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" "" { target *-*-* } 0 } */
-
-#pragma GCC target "+sme"
-
-int main (void)
-{
-  return 0;
-}