clocksource/drivers/sun5i: Add D1 hstimer support

D1 high speed timer differs from existing timer-sun5i by register base
offset.

Add sunxi quirks to handle D1 specific offset.
Add D1 compatible string to OF match table.

Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Link: https://patch.msgid.link/20260428-h616-t113s-hstimer-v3-2-7e02178a93ee@mmpsystems.pl

diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
index d7e012992170b7c03fd337d8961a412ed68b77f9..6ab300d226215fb0f251f208def164e9c0da414c 100644 (file)
--- a/drivers/clocksource/timer-sun5i.c
+++ b/drivers/clocksource/timer-sun5i.c
@@ -18,21 +18,30 @@
 #include <linux/slab.h>
 #include <linux/platform_device.h>
 
-#define TIMER_IRQ_EN_REG               0x00
+#define TIMER_IRQ_EN_REG                       0x00
 #define TIMER_IRQ_EN(val)                      BIT(val)
-#define TIMER_IRQ_ST_REG               0x04
-#define TIMER_CTL_REG(val)             (0x20 * (val) + 0x10)
+#define TIMER_IRQ_ST_REG                       0x04
+#define TIMER_CTL_REG(val, offset)             (0x20 * (val) + 0x10 + (offset))
 #define TIMER_CTL_ENABLE                       BIT(0)
 #define TIMER_CTL_RELOAD                       BIT(1)
 #define TIMER_CTL_CLK_PRES(val)                        (((val) & 0x7) << 4)
 #define TIMER_CTL_ONESHOT                      BIT(7)
-#define TIMER_INTVAL_LO_REG(val)       (0x20 * (val) + 0x14)
-#define TIMER_INTVAL_HI_REG(val)       (0x20 * (val) + 0x18)
-#define TIMER_CNTVAL_LO_REG(val)       (0x20 * (val) + 0x1c)
-#define TIMER_CNTVAL_HI_REG(val)       (0x20 * (val) + 0x20)
+#define TIMER_INTVAL_LO_REG(val, offset)       (0x20 * (val) + 0x14 + (offset))
+#define TIMER_INTVAL_HI_REG(val, offset)       (0x20 * (val) + 0x18 + (offset))
+#define TIMER_CNTVAL_LO_REG(val, offset)       (0x20 * (val) + 0x1c + (offset))
+#define TIMER_CNTVAL_HI_REG(val, offset)       (0x20 * (val) + 0x20 + (offset))
 
 #define TIMER_SYNC_TICKS       3
 
+/**
+ * struct sunxi_timer_quirks - Differences between SoC variants.
+ *
+ * @from_ctl_base_offset: offset applied from ctl register onwards
+ */
+struct sunxi_timer_quirks {
+       u32 from_ctl_base_offset;
+};
+
 struct sun5i_timer {
        void __iomem            *base;
        struct clk              *clk;
@@ -40,6 +49,7 @@ struct sun5i_timer {
        u32                     ticks_per_jiffy;
        struct clocksource      clksrc;
        struct clock_event_device       clkevt;
+       const struct sunxi_timer_quirks *quirks;
 };
 
 #define nb_to_sun5i_timer(x) \
@@ -57,28 +67,36 @@ struct sun5i_timer {
  */
 static void sun5i_clkevt_sync(struct sun5i_timer *ce)
 {
-       u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1));
+       u32 offset = ce->quirks->from_ctl_base_offset;
+       u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset));
 
-       while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
+       while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset))) <
+              TIMER_SYNC_TICKS)
                cpu_relax();
 }
 
 static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer)
 {
-       u32 val = readl(ce->base + TIMER_CTL_REG(timer));
-       writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer));
+       u32 offset = ce->quirks->from_ctl_base_offset;
+       u32 val = readl(ce->base + TIMER_CTL_REG(timer, offset));
+
+       writel(val & ~TIMER_CTL_ENABLE,
+              ce->base + TIMER_CTL_REG(timer, offset));
 
        sun5i_clkevt_sync(ce);
 }
 
 static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 delay)
 {
-       writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer));
+       u32 offset = ce->quirks->from_ctl_base_offset;
+
+       writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer, offset));
 }
 
 static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool periodic)
 {
-       u32 val = readl(ce->base + TIMER_CTL_REG(timer));
+       u32 offset = ce->quirks->from_ctl_base_offset;
+       u32 val = readl(ce->base + TIMER_CTL_REG(timer, offset));
 
        if (periodic)
                val &= ~TIMER_CTL_ONESHOT;
@@ -86,7 +104,7 @@ static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool perio
                val |= TIMER_CTL_ONESHOT;
 
        writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
-              ce->base + TIMER_CTL_REG(timer));
+              ce->base + TIMER_CTL_REG(timer, offset));
 }
 
 static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
@@ -141,8 +159,9 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
 static u64 sun5i_clksrc_read(struct clocksource *clksrc)
 {
        struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc);
+       u32 offset = cs->quirks->from_ctl_base_offset;
 
-       return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1));
+       return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1, offset));
 }
 
 static int sun5i_rate_cb(struct notifier_block *nb,
@@ -173,12 +192,13 @@ static int sun5i_setup_clocksource(struct platform_device *pdev,
                                   unsigned long rate)
 {
        struct sun5i_timer *cs = platform_get_drvdata(pdev);
+       u32 offset = cs->quirks->from_ctl_base_offset;
        void __iomem *base = cs->base;
        int ret;
 
-       writel(~0, base + TIMER_INTVAL_LO_REG(1));
+       writel(~0, base + TIMER_INTVAL_LO_REG(1, offset));
        writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
-              base + TIMER_CTL_REG(1));
+              base + TIMER_CTL_REG(1, offset));
 
        cs->clksrc.name = pdev->dev.of_node->name;
        cs->clksrc.rating = 340;
@@ -237,6 +257,7 @@ static int sun5i_setup_clockevent(struct platform_device *pdev,
 
 static int sun5i_timer_probe(struct platform_device *pdev)
 {
+       const struct sunxi_timer_quirks *quirks;
        struct device *dev = &pdev->dev;
        struct sun5i_timer *st;
        struct reset_control *rstc;
@@ -273,11 +294,18 @@ static int sun5i_timer_probe(struct platform_device *pdev)
                return -EINVAL;
        }
 
+       quirks = of_device_get_match_data(&pdev->dev);
+       if (!quirks) {
+               dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+               return -ENODEV;
+       }
+
        st->base = timer_base;
        st->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
        st->clk = clk;
        st->clk_rate_cb.notifier_call = sun5i_rate_cb;
        st->clk_rate_cb.next = NULL;
+       st->quirks = quirks;
 
        ret = devm_clk_notifier_register(dev, clk, &st->clk_rate_cb);
        if (ret) {
@@ -314,9 +342,27 @@ static void sun5i_timer_remove(struct platform_device *pdev)
        clocksource_unregister(&st->clksrc);
 }
 
+static const struct sunxi_timer_quirks sun5i_sun7i_hstimer_quirks = {
+       .from_ctl_base_offset = 0x0,
+};
+
+static const struct sunxi_timer_quirks sun20i_d1_hstimer_quirks = {
+       .from_ctl_base_offset = 0x10,
+};
+
 static const struct of_device_id sun5i_timer_of_match[] = {
-       { .compatible = "allwinner,sun5i-a13-hstimer" },
-       { .compatible = "allwinner,sun7i-a20-hstimer" },
+       {
+               .compatible = "allwinner,sun5i-a13-hstimer",
+               .data = &sun5i_sun7i_hstimer_quirks,
+       },
+       {
+               .compatible = "allwinner,sun7i-a20-hstimer",
+               .data = &sun5i_sun7i_hstimer_quirks,
+       },
+       {
+               .compatible = "allwinner,sun20i-d1-hstimer",
+               .data = &sun20i_d1_hstimer_quirks,
+       },
        {},
 };
 MODULE_DEVICE_TABLE(of, sun5i_timer_of_match);