net: enetc: Remove CBDR cacheability AXI settings for ENETC v4

[ Upstream commit 9ae13b2e64fcd2ca00a76b7d60fc4641a6b9209d ]

For ENETC v4 these settings are controlled by the global ENETC
command cache attribute registers (EnCAR), from the IERB register
block.

The hardcoded CDBR cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.

Fixes: e3f4a0a8ddb4 ("net: enetc: add command BD ring support for i.MX95 ENETC")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Link: https://patch.msgid.link/20260130141035.272471-3-claudiu.manoil@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
index 3d5f31879d5c64bfc853bb4e7f99d3963b867e32..a635bfdc30afc295d5b4592c23b96ebe43a19dbc 100644 (file)
--- a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
@@ -74,10 +74,6 @@ int enetc4_setup_cbdr(struct enetc_si *si)
        if (!user->ring)
                return -ENOMEM;
 
-       /* set CBDR cache attributes */
-       enetc_wr(hw, ENETC_SICAR2,
-                ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
-
        regs.pir = hw->reg + ENETC_SICBDRPIR;
        regs.cir = hw->reg + ENETC_SICBDRCIR;
        regs.mr = hw->reg + ENETC_SICBDRMR;