mtd: spi-nor: winbond: Add W25Q01NWxxIQ CMP locking support

This chip has support for the locking complement (CMP) feature. Add
the relevant bit to enable it.

Unfortunately, this chip also comes with an incorrect BFPT table,
indicating the Control Register cannot be read back. This is wrong,
reading back the register works and has no (observed) side effect. The
datasheet clearly indicates supporting the 35h command and all bits from
the CR are marked readable. QE and CMP bits are inside, and can be
properly read back.

Add a fixup for this, otherwise it would defeat the use of the CMP
feature.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>

diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 2c48d6c4a0aa512b5cc0a76c90ba05f643f12f43..3eca7baa4d5acfe2a597128587f4b8fa8dbdf6a8 100644 (file)
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -368,7 +368,9 @@ static const struct flash_info winbond_nor_parts[] = {
        }, {
                /* W25Q01NWxxIQ */
                .id = SNOR_ID(0xef, 0x60, 0x21),
-               .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP,
+               .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+                        SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
+               .fixups = &winbond_rdcr_fixup,
        }, {
                /* W25Q01NWxxIM */
                .id = SNOR_ID(0xef, 0x80, 0x21),