* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
clock-frequency = <27000000>;
clock-output-names = "aux_ref_clk";
};
+
+ rtc_clk: rtc-clk {
+ bootph-all;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "rtc_clk";
+ };
};
&zynqmp_firmware {
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
};
+
+&rtc {
+ clocks = <&rtc_clk>;
+ clock-names = "rtc";
+};
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "sec";
- calibration = <0x7FFF>;
};
sata: ahci@fd0c0000 {