]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arch: arm: dts: Add RTC clock nodes for ZynqMP platform
authorHarini T <harini.t@amd.com>
Mon, 29 Jun 2026 09:46:33 +0000 (11:46 +0200)
committerMichal Simek <michal.simek@amd.com>
Wed, 8 Jul 2026 06:55:52 +0000 (08:55 +0200)
Add fixed RTC clock nodes at 32.768 kHz for ZynqMP. The RTC driver uses
this clock to calculate the calibration value, replacing the deprecated
calibration device tree property.

Signed-off-by: Harini T <harini.t@amd.com>
Reviewed-by: Tomas Melin <tomas.melin@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/8838c8c4fcd0dfe151bcee2a6c4da51df81e23cb.1782726386.git.michal.simek@amd.com
arch/arm/dts/zynqmp-clk-ccf.dtsi
arch/arm/dts/zynqmp.dtsi

index 482f432ba7f3d313d4f4b674e9b5878bd2d1cbf8..877962df2b36d4ac99840441e169d9b841105a6a 100644 (file)
@@ -3,7 +3,7 @@
  * Clock specification for Xilinx ZynqMP
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
                clock-frequency = <27000000>;
                clock-output-names = "aux_ref_clk";
        };
+
+       rtc_clk: rtc-clk {
+               bootph-all;
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               clock-output-names = "rtc_clk";
+       };
 };
 
 &zynqmp_firmware {
                          <&zynqmp_clk DP_AUDIO_REF>,
                          <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */
 };
+
+&rtc {
+       clocks = <&rtc_clk>;
+       clock-names = "rtc";
+};
index 13cfca666572ff4bcb8005d6eea00cafce9e5e54..c225eb219f4cb46efa7e87f4e77865ac8b84523c 100644 (file)
                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "alarm", "sec";
-                       calibration = <0x7FFF>;
                };
 
                sata: ahci@fd0c0000 {