* http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
* For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
*/
- err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
+ err = rdmsrq_safe_on_cpu(id, 0x17, &val);
if (err) {
dev_warn(dev,
- "Unable to access MSR 0x17, assuming desktop"
- " CPU\n");
+ "Unable to access MSR 0x17, assuming desktop CPU\n");
usemsr_ee = 0;
} else if (c->x86_vfm < INTEL_CORE2_PENRYN &&
- !(eax & 0x10000000)) {
+ !(val & 0x10000000)) {
/*
* Trust bit 28 up to Penryn, I could not find any
* documentation on that; if you happen to know
}
if (usemsr_ee) {
- err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
+ err = rdmsrq_safe_on_cpu(id, 0xee, &val);
if (err) {
dev_warn(dev,
- "Unable to access MSR 0xEE, for Tjmax, left"
- " at default\n");
+ "Unable to access MSR 0xEE, for Tjmax, left at default\n");
- } else if (eax & 0x40000000) {
+ } else if (val & 0x40000000) {
tjmax = tjmax_ee;
}
} else if (tjmax == 100000) {
}
static ssize_t show_crit_alarm(struct device *dev,
- struct device_attribute *devattr, char *buf)
+ struct device_attribute *devattr, char *buf)
{
- u32 eax, edx;
+ struct msr val;
struct temp_data *tdata = container_of(devattr, struct temp_data,
sd_attrs[ATTR_CRIT_ALARM]);
}
static ssize_t show_temp(struct device *dev,
- struct device_attribute *devattr, char *buf)
+ struct device_attribute *devattr, char *buf)
{
- u32 eax, edx;
+ struct msr val;
struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TEMP]);
int tjmax;