drm/amd: Disable DP audio spread spectrum for Cyan Skillfish

The VBIOS for Cyan Skillfish devices (DCN201) indicates there is
DisplayPort ref clock spread spectrum downspread, so the audio clock
is corrected for it.

However, the clock source in this hardware does not seem to actually be
running with a clock downspread, so DisplayPort audio desyncs with video
after several minutes.

Ignore dprefclk SS downspread on CYAN_SKILLFISH2 asic.

Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5429
Signed-off-by: Travis K. Bangs <tbangs89@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit f3a2d86587432fdd9a6d401507b60a01153453c5)
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1820547b1dde8094bfe97b5e77af57348041f8e8..941c1a3128249865b990a3692611c092240b41c4 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2189,6 +2189,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
                init_data.flags.unify_link_enc_assignment = true;
                init_data.flags.usb4_bw_alloc_support = true;
        }
+
+       /* DCN201 audio desyncs using DP SS */
+       if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
+               init_data.flags.ignore_dpref_ss = true;
+
        retrieve_dmi_info(&adev->dm);
        if (adev->dm.edp0_on_dp1_quirk)
                init_data.flags.support_edp0_on_dp1 = true;