};
enet0: ethernet@b0000 {
- status = "okay";
phy-connection-type = "rgmii-id";
nvmem-cells = <&macaddr_hwinfo_0 0>;
nvmem-cell-names = "mac-address";
};
pci0: pcie@ffe09000 {
+ reg = <0 0xffe09000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+
status = "disabled";
+
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
};
pci1: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
- 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+ 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
pci0: pcie@ffe09000 {
+ reg = <0 0xffe09000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+
status = "disabled";
+
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+
};
pci1: pcie@ffe0a000 {
d-cache-sets = <0x80>;
d-cache-size = <0x8000>;
d-cache-block-size = <0x20>;
- status = "okay";
clock-frequency = <533333328>; /* 533.33 MHz */
bus-frequency = <266666664>; /* 266.66 MHz */
timebase-frequency = <33333333>; /* 33.33 MHz */
ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
nor@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
rx-stash-idx = <0x00>;
rx-stash-len = <0x60>;
bd-stash;
- status = "okay";
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
nvmem-cells = <&macaddr_hwinfo_0 0>;
rx-stash-idx = <0x00>;
rx-stash-len = <0x60>;
bd-stash;
- status = "okay";
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
nvmem-cells = <&macaddr_hwinfo_0 1>;
};
pci0: pcie@ffe09000 {
+ reg = <0 0xffe09000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+
status = "disabled";
+
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
};
pci1: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
};
ifc: ifc@ffe1e000 {
+ reg = <0x0 0xffe1e000 0 0x2000>;
+
status = "disabled";
};
ranges = <0x0 0x0 0x0 0xee000000 0x2000000>;
nor@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
i-cache-size = <0x8000>;
i-cache-sets = <0x80>;
cpu-release-addr = <0x0 0x0ffff280>;
- status = "okay";
enable-method = "spin-table";
};
};
ifc: ifc@ffe1e000 {
+ reg = <0x0 0xffe1e000 0 0x2000>;
+
+ status = "disabled";
};
pci0: pcie@ffe09000 {
ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
nor@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
};
enet0: ethernet@b0000 {
- status = "okay";
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
};
enet2: ethernet@b2000 {
- status = "okay";
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
i-cache-size = <0x8000>;
i-cache-sets = <0x80>;
cpu-release-addr = <0x0 0x0ffff280>;
- status = "okay";
enable-method = "spin-table";
};