/dts-v1/;
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
- clocks = <&sysc 7>;
+ clocks = <&sysc MT7620_CLK_TIMER>;
interrupt-parent = <&intc>;
interrupts = <1>;
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- clocks = <&sysc 8>;
+ clocks = <&sysc MT7620_CLK_WATCHDOG>;
resets = <&sysc 8>;
reset-names = "wdt";
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- clocks = <&sysc 9>;
+ clocks = <&sysc MT7620_CLK_UART>;
resets = <&sysc 12>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc 10>;
+ clocks = <&sysc MT7620_CLK_I2C>;
resets = <&sysc 16>;
reset-names = "i2c";
compatible = "mediatek,mt7620-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysc 11>;
+ clocks = <&sysc MT7620_CLK_I2S>;
resets = <&sysc 17>;
reset-names = "i2s";
compatible = "ralink,rt2880-spi";
reg = <0xb00 0x40>;
- clocks = <&sysc 12>;
+ clocks = <&sysc MT7620_CLK_SPI1>;
resets = <&sysc 18>;
reset-names = "spi";
compatible = "ralink,rt2880-spi";
reg = <0xb40 0x60>;
- clocks = <&sysc 13>;
+ clocks = <&sysc MT7620_CLK_SPI2>;
resets = <&sysc 18>;
reset-names = "spi";
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysc 14>;
+ clocks = <&sysc MT7620_CLK_UARTLITE>;
resets = <&sysc 19>;
disable-wp;
no-1-8-v;
- clocks = <&sysc 15>, <&sysc 15>;
+ clocks = <&sysc MT7620_CLK_MMC>, <&sysc MT7620_CLK_MMC>;
clock-names = "source", "hclk";
interrupt-parent = <&intc>;
compatible = "ralink,rt7620-wifi", "ralink,rt2880-wifi";
reg = <0x10180000 0x40000>;
- clocks = <&sysc 16>;
+ clocks = <&sysc MT7620_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
/dts-v1/;
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
- clocks = <&sysc 7>;
+ clocks = <&sysc MT7620_CLK_TIMER>;
interrupt-parent = <&intc>;
interrupts = <1>;
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- clocks = <&sysc 8>;
+ clocks = <&sysc MT7620_CLK_WATCHDOG>;
resets = <&sysc 8>;
reset-names = "wdt";
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc 10>;
+ clocks = <&sysc MT7620_CLK_I2C>;
resets = <&sysc 16>;
reset-names = "i2c";
compatible = "ralink,rt2880-spi";
reg = <0xb00 0x40>;
- clocks = <&sysc 12>;
+ clocks = <&sysc MT7620_CLK_SPI1>;
resets = <&sysc 18>;
reset-names = "spi";
compatible = "ralink,rt2880-spi";
reg = <0xb40 0x60>;
- clocks = <&sysc 13>;
+ clocks = <&sysc MT7620_CLK_SPI2>;
resets = <&sysc 18>;
reset-names = "spi";
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysc 14>;
+ clocks = <&sysc MT7620_CLK_UARTLITE>;
resets = <&sysc 19>;
compatible = "ralink,rt7620-wifi", "ralink,rt2880-wifi";
reg = <0x10180000 0x40000>;
- clocks = <&sysc 16>;
+ clocks = <&sysc MT7620_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
/dts-v1/;
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc 9>;
+ clocks = <&sysc MT76X8_CLK_I2C>;
clock-names = "i2c";
resets = <&sysc 16>;
compatible = "mediatek,mt7628-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysc 10>;
+ clocks = <&sysc MT76X8_CLK_I2S>;
resets = <&sysc 17>;
reset-names = "i2s";
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&sysc 11>;
+ clocks = <&sysc MT76X8_CLK_SPI1>;
clock-names = "spi";
resets = <&sysc 18>;
reg-io-width = <4>;
no-loopback-test;
- clocks = <&sysc 13>;
+ clocks = <&sysc MT76X8_CLK_UART0>;
resets = <&sysc 12>;
reg-io-width = <4>;
no-loopback-test;
- clocks = <&sysc 14>;
+ clocks = <&sysc MT76X8_CLK_UART1>;
resets = <&sysc 19>;
reg-io-width = <4>;
no-loopback-test;
- clocks = <&sysc 15>;
+ clocks = <&sysc MT76X8_CLK_UART2>;
resets = <&sysc 20>;
disable-wp;
no-1-8-v;
- clocks = <&sysc 16>, <&sysc 16>;
+ clocks = <&sysc MT76X8_CLK_MMC>, <&sysc MT76X8_CLK_MMC>;
clock-names = "source", "hclk";
interrupt-parent = <&intc>;
compatible = "mediatek,mt7628-wmac";
reg = <0x10300000 0x100000>;
- clocks = <&sysc 17>;
+ clocks = <&sysc MT76X8_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
/dts-v1/;
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
- clocks = <&sysc 3>;
+ clocks = <&sysc RT2880_CLK_TIMER>;
interrupt-parent = <&intc>;
interrupts = <1>;
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- clocks = <&sysc 4>;
+ clocks = <&sysc RT2880_CLK_WATCHDOG>;
};
intc: intc@200 {
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc 6>;
+ clocks = <&sysc RT2880_CLK_I2C>;
resets = <&sysc 9>;
reset-names = "i2c";
compatible = "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysc 7>;
+ clocks = <&sysc RT2880_CLK_UARTLITE>;
interrupt-parent = <&intc>;
interrupts = <8>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&sysc 8>;
+ clocks = <&sysc RT2880_CLK_ETHERNET>;
resets = <&sysc 18>;
reset-names = "fe";
compatible = "ralink,rt2880-wifi";
reg = <0x480000 0x40000>;
- clocks = <&sysc 9>;
+ clocks = <&sysc RT2880_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
/dts-v1/;
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
- clocks = <&sysc 3>;
+ clocks = <&sysc RT305X_CLK_TIMER>;
interrupt-parent = <&intc>;
interrupts = <1>;
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- clocks = <&sysc 4>;
+ clocks = <&sysc RT305X_CLK_WATCHDOG>;
resets = <&sysc 8>;
reset-names = "wdt";
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- clocks = <&sysc 5>;
+ clocks = <&sysc RT305X_CLK_UART>;
resets = <&sysc 12>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc 6>;
+ clocks = <&sysc RT305X_CLK_I2C>;
resets = <&sysc 16>;
reset-names = "i2c";
compatible = "ralink,rt3050-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysc 7>;
+ clocks = <&sysc RT305X_CLK_I2S>;
resets = <&sysc 17>;
reset-names = "i2s";
resets = <&sysc 18>;
reset-names = "spi";
- clocks = <&sysc 8>;
+ clocks = <&sysc RT305X_CLK_SPI1>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysc 10>;
+ clocks = <&sysc RT305X_CLK_UARTLITE>;
resets = <&sysc 19>;
compatible = "ralink,rt3050-eth";
reg = <0x10100000 0x10000>;
- clocks = <&sysc 11>;
+ clocks = <&sysc RT305X_CLK_ETHERNET>;
resets = <&sysc 21>, <&sysc 23>;
reset-names = "fe", "esw";
compatible = "ralink,rt3050-wifi", "ralink,rt2880-wifi";
reg = <0x10180000 0x40000>;
- clocks = <&sysc 12>;
+ clocks = <&sysc RT305X_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
/dts-v1/;
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
- clocks = <&sysc 4>;
+ clocks = <&sysc RT3352_CLK_TIMER>;
interrupt-parent = <&intc>;
interrupts = <1>;
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- clocks = <&sysc 5>;
+ clocks = <&sysc RT3352_CLK_WATCHDOG>;
resets = <&sysc 8>;
reset-names = "wdt";
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- clocks = <&sysc 6>;
+ clocks = <&sysc RT3352_CLK_UART>;
resets = <&sysc 12>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc 7>;
+ clocks = <&sysc RT3352_CLK_I2C>;
resets = <&sysc 16>;
reset-names = "i2c";
compatible = "ralink,rt3352-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysc 8>;
+ clocks = <&sysc RT3352_CLK_I2S>;
resets = <&sysc 17>;
reset-names = "i2s";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&sysc 9>;
+ clocks = <&sysc RT3352_CLK_SPI1>;
resets = <&sysc 18>;
reset-names = "spi";
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysc 11>;
+ clocks = <&sysc RT3352_CLK_UARTLITE>;
resets = <&sysc 19>;
compatible = "ralink,rt3050-eth";
reg = <0x10100000 0x10000>;
- clocks = <&sysc 12>;
+ clocks = <&sysc RT3352_CLK_ETHERNET>;
resets = <&sysc 21>, <&sysc 23>;
reset-names = "fe", "esw";
compatible = "ralink,rt3352-wifi", "ralink,rt2880-wifi";
reg = <0x10180000 0x40000>;
- clocks = <&sysc 13>;
+ clocks = <&sysc RT3352_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
/dts-v1/;
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
- clocks = <&sysc 4>;
+ clocks = <&sysc RT3883_CLK_TIMER>;
interrupt-parent = <&intc>;
interrupts = <1>;
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- clocks = <&sysc 5>;
+ clocks = <&sysc RT3883_CLK_WATCHDOG>;
resets = <&sysc 8>;
reset-names = "wdt";
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- clocks = <&sysc 6>;
+ clocks = <&sysc RT3883_CLK_UART>;
resets = <&sysc 12>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc 7>;
+ clocks = <&sysc RT3883_CLK_I2C>;
resets = <&sysc 16>;
reset-names = "i2c";
compatible = "ralink,rt3883-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysc 8>;
+ clocks = <&sysc RT3883_CLK_I2S>;
resets = <&sysc 17>;
reset-names = "i2s";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&sysc 9>;
+ clocks = <&sysc RT3883_CLK_SPI1>;
resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&sysc 10>;
+ clocks = <&sysc RT3883_CLK_SPI2>;
resets = <&sysc 18>;
reset-names = "spi";
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysc 11>;
+ clocks = <&sysc RT3883_CLK_UARTLITE>;
resets = <&sysc 19>;
#size-cells = <0>;
reg = <0x10100000 0x10000>;
- clocks = <&sysc 12>;
+ clocks = <&sysc RT3883_CLK_ETHERNET>;
resets = <&sysc 21>;
reset-names = "fe";
compatible = "ralink,rt3883-wifi", "ralink,rt2880-wifi";
reg = <0x10180000 0x40000>;
- clocks = <&sysc 13>;
+ clocks = <&sysc RT3883_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
/dts-v1/;
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>;
- clocks = <&sysc 4>;
+ clocks = <&sysc RT5350_CLK_TIMER>;
interrupt-parent = <&intc>;
interrupts = <1>;
compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>;
- clocks = <&sysc 5>;
+ clocks = <&sysc RT5350_CLK_WATCHDOG>;
resets = <&sysc 8>;
reset-names = "wdt";
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>;
- clocks = <&sysc 6>;
+ clocks = <&sysc RT5350_CLK_UART>;
resets = <&sysc 12>;
compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc 7>;
+ clocks = <&sysc RT5350_CLK_I2C>;
resets = <&sysc 16>;
reset-names = "i2c";
compatible = "ralink,rt3352-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysc 8>;
+ clocks = <&sysc RT5350_CLK_I2S>;
resets = <&sysc 17>;
reset-names = "i2s";
compatible = "ralink,rt2880-spi";
reg = <0xb00 0x40>;
- clocks = <&sysc 9>;
+ clocks = <&sysc RT5350_CLK_SPI1>;
resets = <&sysc 18>;
reset-names = "spi";
compatible = "ralink,rt2880-spi";
reg = <0xb40 0x60>;
- clocks = <&sysc 10>;
+ clocks = <&sysc RT5350_CLK_SPI2>;
resets = <&sysc 18>;
reset-names = "spi";
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysc 11>;
+ clocks = <&sysc RT5350_CLK_UARTLITE>;
resets = <&sysc 19>;
compatible = "ralink,rt5350-eth";
reg = <0x10100000 0x10000>;
- clocks = <&sysc 12>;
+ clocks = <&sysc RT5350_CLK_ETHERNET>;
resets = <&sysc 21>, <&sysc 23>;
reset-names = "fe", "esw";
compatible = "ralink,rt5350-wifi", "ralink,rt2880-wifi";
reg = <0x10180000 0x40000>;
- clocks = <&sysc 13>;
+ clocks = <&sysc RT5350_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
--- /dev/null
+From adb2424d0d05506c2f36fcba66101d34f7409e45 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 20 Jan 2025 10:21:41 +0100
+Subject: [PATCH] dt-bindings: clock: add clock definitions for Ralink SoCs
+
+Add clock missing definitions for RT2880, RT305X, RT3352, RT3383, RT5350,
+MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock depending
+on these new introduced constants so consumer nodes can easily use the
+correct one in DTS files matching properly what is being used in driver
+code (clock IDs are implicitly used there).
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+ .../bindings/clock/mediatek,mtmips-sysc.yaml | 11 +-
+ .../dt-bindings/clock/mediatek,mtmips-sysc.h | 130 ++++++++++++++++++
+ 2 files changed, 140 insertions(+), 1 deletion(-)
+ create mode 100644 include/dt-bindings/clock/mediatek,mtmips-sysc.h
+
+--- a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+@@ -18,6 +18,12 @@ description: |
+ These SoCs have an XTAL from where the cpu clock is
+ provided as well as derived clocks for the bus and the peripherals.
+
++ Each clock is assigned an identifier and client nodes use this identifier
++ to specify the clock which they consume.
++
++ All these identifiers could be found in:
++ [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
++
+ properties:
+ compatible:
+ items:
+@@ -38,7 +44,8 @@ properties:
+
+ '#clock-cells':
+ description:
+- The first cell indicates the clock number.
++ The first cell indicates the clock number, see [1] for available
++ clocks.
+ const: 1
+
+ '#reset-cells':
+@@ -56,6 +63,8 @@ additionalProperties: false
+
+ examples:
+ - |
++ #include <dt-bindings/clock/mediatek,mtmips-sysc.h>
++
+ syscon@0 {
+ compatible = "ralink,rt5350-sysc", "syscon";
+ reg = <0x0 0x100>;
+--- /dev/null
++++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
+@@ -0,0 +1,130 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
++ */
++
++#ifndef _DT_BINDINGS_CLK_MTMIPS_H
++#define _DT_BINDINGS_CLK_MTMIPS_H
++
++/* Ralink RT-2880 clocks */
++
++#define RT2880_CLK_XTAL 0
++#define RT2880_CLK_CPU 1
++#define RT2880_CLK_BUS 2
++#define RT2880_CLK_TIMER 3
++#define RT2880_CLK_WATCHDOG 4
++#define RT2880_CLK_UART 5
++#define RT2880_CLK_I2C 6
++#define RT2880_CLK_UARTLITE 7
++#define RT2880_CLK_ETHERNET 8
++#define RT2880_CLK_WMAC 9
++
++/* Ralink RT-305X clocks */
++
++#define RT305X_CLK_XTAL 0
++#define RT305X_CLK_CPU 1
++#define RT305X_CLK_BUS 2
++#define RT305X_CLK_TIMER 3
++#define RT305X_CLK_WATCHDOG 4
++#define RT305X_CLK_UART 5
++#define RT305X_CLK_I2C 6
++#define RT305X_CLK_I2S 7
++#define RT305X_CLK_SPI1 8
++#define RT305X_CLK_SPI2 9
++#define RT305X_CLK_UARTLITE 10
++#define RT305X_CLK_ETHERNET 11
++#define RT305X_CLK_WMAC 12
++
++/* Ralink RT-3352 clocks */
++
++#define RT3352_CLK_XTAL 0
++#define RT3352_CLK_CPU 1
++#define RT3352_CLK_PERIPH 2
++#define RT3352_CLK_BUS 3
++#define RT3352_CLK_TIMER 4
++#define RT3352_CLK_WATCHDOG 5
++#define RT3352_CLK_UART 6
++#define RT3352_CLK_I2C 7
++#define RT3352_CLK_I2S 8
++#define RT3352_CLK_SPI1 9
++#define RT3352_CLK_SPI2 10
++#define RT3352_CLK_UARTLITE 11
++#define RT3352_CLK_ETHERNET 12
++#define RT3352_CLK_WMAC 13
++
++/* Ralink RT-3883 clocks */
++
++#define RT3883_CLK_XTAL 0
++#define RT3883_CLK_CPU 1
++#define RT3883_CLK_BUS 2
++#define RT3883_CLK_PERIPH 3
++#define RT3883_CLK_TIMER 4
++#define RT3883_CLK_WATCHDOG 5
++#define RT3883_CLK_UART 6
++#define RT3883_CLK_I2C 7
++#define RT3883_CLK_I2S 8
++#define RT3883_CLK_SPI1 9
++#define RT3883_CLK_SPI2 10
++#define RT3883_CLK_UARTLITE 11
++#define RT3883_CLK_ETHERNET 12
++#define RT3883_CLK_WMAC 13
++
++/* Ralink RT-5350 clocks */
++
++#define RT5350_CLK_XTAL 0
++#define RT5350_CLK_CPU 1
++#define RT5350_CLK_BUS 2
++#define RT5350_CLK_PERIPH 3
++#define RT5350_CLK_TIMER 4
++#define RT5350_CLK_WATCHDOG 5
++#define RT5350_CLK_UART 6
++#define RT5350_CLK_I2C 7
++#define RT5350_CLK_I2S 8
++#define RT5350_CLK_SPI1 9
++#define RT5350_CLK_SPI2 10
++#define RT5350_CLK_UARTLITE 11
++#define RT5350_CLK_ETHERNET 12
++#define RT5350_CLK_WMAC 13
++
++/* Ralink MT-7620 clocks */
++
++#define MT7620_CLK_XTAL 0
++#define MT7620_CLK_PLL 1
++#define MT7620_CLK_CPU 2
++#define MT7620_CLK_PERIPH 3
++#define MT7620_CLK_BUS 4
++#define MT7620_CLK_BBPPLL 5
++#define MT7620_CLK_SDHC 6
++#define MT7620_CLK_TIMER 7
++#define MT7620_CLK_WATCHDOG 8
++#define MT7620_CLK_UART 9
++#define MT7620_CLK_I2C 10
++#define MT7620_CLK_I2S 11
++#define MT7620_CLK_SPI1 12
++#define MT7620_CLK_SPI2 13
++#define MT7620_CLK_UARTLITE 14
++#define MT7620_CLK_MMC 15
++#define MT7620_CLK_WMAC 16
++
++/* Ralink MT-76X8 clocks */
++
++#define MT76X8_CLK_XTAL 0
++#define MT76X8_CLK_CPU 1
++#define MT76X8_CLK_BBPPLL 2
++#define MT76X8_CLK_PCMI2S 3
++#define MT76X8_CLK_PERIPH 4
++#define MT76X8_CLK_BUS 5
++#define MT76X8_CLK_SDHC 6
++#define MT76X8_CLK_TIMER 7
++#define MT76X8_CLK_WATCHDOG 8
++#define MT76X8_CLK_I2C 9
++#define MT76X8_CLK_I2S 10
++#define MT76X8_CLK_SPI1 11
++#define MT76X8_CLK_SPI2 12
++#define MT76X8_CLK_UART0 13
++#define MT76X8_CLK_UART1 14
++#define MT76X8_CLK_UART2 15
++#define MT76X8_CLK_MMC 16
++#define MT76X8_CLK_WMAC 17
++
++#endif /* _DT_BINDINGS_CLK_MTMIPS_H */
projects / thirdparty / openwrt.git / commitdiff
