airoha: Add PCIe sub-nodes for NPU wifi offloading

Introduce missing PCIe sub-nodes required to enable NPU wifi offloading
on Airoha AN7581 SoC.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://github.com/openwrt/openwrt/pull/22516
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/target/linux/airoha/dts/an7581-evb-emmc.dts b/target/linux/airoha/dts/an7581-evb-emmc.dts
index d78bbb1bd2256e709c9cfefbdf17adc82cf62d3d..25aca81e2242e6015bbc19d167453fbb9a1b380a 100644 (file)
--- a/target/linux/airoha/dts/an7581-evb-emmc.dts
+++ b/target/linux/airoha/dts/an7581-evb-emmc.dts
@@ -184,12 +184,32 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pcie0_rst_pins>;
        status = "okay";
+
+       pcie@0,0 {
+               reg = <0x0000 0 0 0 0>;
+               wifi@0,0 {
+                       compatible = "mediatek,mt76";
+                       reg = <0x0000 0 0 0 0>;
+                       airoha,npu = <&npu>;
+                       airoha,eth = <&eth>;
+               };
+       };
 };
 
 &pcie1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pcie1_rst_pins>;
        status = "okay";
+
+       pcie@1,0 {
+               reg = <0x0000 0 0 0 0>;
+               wifi@0,0 {
+                       compatible = "mediatek,mt76";
+                       reg = <0x0000 0 0 0 0>;
+                       airoha,npu = <&npu>;
+                       airoha,eth = <&eth>;
+               };
+       };
 };
 
 &pcie2 {

diff --git a/target/linux/airoha/dts/an7581-evb.dts b/target/linux/airoha/dts/an7581-evb.dts
index 8d52b92636ec5a68704ada050cd1c289417f3f22..eea7bea586027ebc775d5fc103bc35b7afdcac45 100644 (file)
--- a/target/linux/airoha/dts/an7581-evb.dts
+++ b/target/linux/airoha/dts/an7581-evb.dts
@@ -196,12 +196,32 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pcie0_rst_pins>;
        status = "okay";
+
+       pcie@0,0 {
+               reg = <0x0000 0 0 0 0>;
+               wifi@0,0 {
+                       compatible = "mediatek,mt76";
+                       reg = <0x0000 0 0 0 0>;
+                       airoha,npu = <&npu>;
+                       airoha,eth = <&eth>;
+               };
+       };
 };
 
 &pcie1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pcie1_rst_pins>;
        status = "okay";
+
+       pcie@1,0 {
+               reg = <0x0000 0 0 0 0>;
+               wifi@0,0 {
+                       compatible = "mediatek,mt76";
+                       reg = <0x0000 0 0 0 0>;
+                       airoha,npu = <&npu>;
+                       airoha,eth = <&eth>;
+               };
+       };
 };
 
 &npu {