From: Dmitry Baryshkov Date: Mon, 12 Jan 2026 02:12:23 +0000 (+0200) Subject: clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source X-Git-Tag: v7.1-rc1~59^2~3^2 X-Git-Url: http://git.ipfire.org/gitweb/?a=commitdiff_plain;h=141af1be817c42c7f1e1605348d4b1983d319bea;p=thirdparty%2Fkernel%2Flinux.git clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source The clk_dp_ops are supposed to be used for DP-related clocks with a proper MND divier. Use standard RCG2 ops for dptx1_aux_clk_src, the same as all other DPTX AUX clocks in this driver. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Taniya Das Link: https://lore.kernel.org/r/20260112-dp-aux-clks-v1-2-456b0c11b069@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index 9ce9fd28e55b2..2e91332dd92ab 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_dp_ops, + .ops = &clk_rcg2_ops, }, };