From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Wed, 24 Jan 2018 11:50:33 +0000 (+0530)
Subject: spi: zynq_qspi: Correct baud rate divisor calculation
X-Git-Url: http://git.ipfire.org/gitweb/?a=commitdiff_plain;h=18340a662aceff0a2b159fa9bf96dd4237d9b17f;p=thirdparty%2Fu-boot.git

spi: zynq_qspi: Correct baud rate divisor calculation

This patch corrects the baud rate divisor calculation by
checking with max baud rate value and assigning default
baud rate value if it exceeds max value.
This fixes the issue of qspi flash detection as writing
the overflown value results in setting unintended bits
in the register.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 4f2d95c6758..12cba4a6b9a 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -99,6 +99,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_MIO_NUM_QSPI1_DIO	3
 #define ZYNQ_QSPI_MIO_NUM_QSPI1_CS_DIO	1
 
+#define ZYNQ_QSPI_MAX_BAUD_RATE		0x7
+#define ZYNQ_QSPI_DEFAULT_BAUD_RATE	0x2
+
 /* QSPI register offsets */
 struct zynq_qspi_regs {
 	u32 confr;	/* 0x00 */
@@ -356,6 +359,9 @@ static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
 		       (2 << baud_rate_val)) > speed))
 			baud_rate_val++;
 
+		if (baud_rate_val > ZYNQ_QSPI_MAX_BAUD_RATE)
+			baud_rate_val = ZYNQ_QSPI_DEFAULT_BAUD_RATE;
+
 		plat->speed_hz = speed / (2 << baud_rate_val);
 	}
 	confr &= ~ZYNQ_QSPI_CONFIG_BAUD_DIV_MASK;