From: Marek Vasut Date: Tue, 5 May 2026 03:42:48 +0000 (+0200) Subject: arm64: dts: renesas: ebisu: Specify ethernet PHY reset timings X-Git-Url: http://git.ipfire.org/gitweb/?a=commitdiff_plain;h=1978e91b4c74b42067b19848d1dc28fd3da4e0f4;p=thirdparty%2Flinux.git arm64: dts: renesas: ebisu: Specify ethernet PHY reset timings The KSZ9031RNX reference manual [1] DS00002117K page 62 FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING Note 2 states, that after the de-assertion of reset, wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) interface. Set DT property reset-deassert-us to three times that, 300 us, to provide ample time between reset deassertion and MDIO access. The KSZ9031RNX reference manual [1] DS00002117K page 62 TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS row tSR Stable supply voltages to de-assertion of reset is at minimum 10 ms. Set DT property reset-assert-us to 10ms because the KSZ9031RNX RM does not explicitly spell out how long the reset has to be asserted, but this at least covers the worst case scenario. [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/KSZ9031RNX-Data-Sheet-DS00002117.pdf Signed-off-by: Marek Vasut Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260505034325.167797-8-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index add60324e0e4a..4b3775afcb017 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -322,6 +322,8 @@ reg = <0>; interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; /* * TX clock internal delay mode is required for reliable * 1Gbps communication using the KSZ9031RNX phy present on