From: Tomer Maimon Date: Tue, 9 Jun 2026 16:39:19 +0000 (+0300) Subject: spi: dt-bindings: nuvoton,npcm750-fiu: Convert to DT schema X-Git-Url: http://git.ipfire.org/gitweb/?a=commitdiff_plain;h=3da90b29241d5a08e689e87c2c76712a63acfb47;p=thirdparty%2Flinux.git spi: dt-bindings: nuvoton,npcm750-fiu: Convert to DT schema Convert the Nuvoton NPCM FIU binding to DT schema format. Document the required control registers and the optional direct- mapped flash window separately, matching the driver behavior when the direct mapping is not described. Signed-off-by: Tomer Maimon Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260609163919.3321228-4-tmaimon77@gmail.com Signed-off-by: Mark Brown --- diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt deleted file mode 100644 index fb38e96d395fb..0000000000000 --- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Nuvoton FLASH Interface Unit (FIU) SPI Controller - -NPCM FIU supports single, dual and quad communication interface. - -The NPCM7XX supports three FIU modules, -FIU0 and FIUx supports two chip selects, -FIU3 support four chip select. - -The NPCM8XX supports four FIU modules, -FIU0 and FIUx supports two chip selects, -FIU1 and FIU3 supports four chip selects. - -Required properties: - - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC - "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC - - #address-cells : should be 1. - - #size-cells : should be 0. - - reg : the first contains the register location and length, - the second contains the memory mapping address and length - - reg-names: Should contain the reg names "control" and "memory" - - clocks : phandle of FIU reference clock. - -Required properties in case the pins can be muxed: - - pinctrl-names : a pinctrl state named "default" must be defined. - - pinctrl-0 : phandle referencing pin configuration of the device. - -Optional property: - - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. - -Aliases: -- All the FIU controller nodes should be represented in the aliases node using - the following format 'fiu{n}' where n is a unique number for the alias. - In the NPCM7XX BMC: - fiu0 represent fiu 0 controller - fiu1 represent fiu 3 controller - fiu2 represent fiu x controller - - In the NPCM8XX BMC: - fiu0 represent fiu 0 controller - fiu1 represent fiu 1 controller - fiu2 represent fiu 3 controller - fiu3 represent fiu x controller - -Example: -fiu3: spi@c00000000 { - compatible = "nuvoton,npcm750-fiu"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; - reg-names = "control", "memory"; - clocks = <&clk NPCM7XX_CLK_AHB>; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins>; - flash@0 { - ... - }; -}; - diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml new file mode 100644 index 0000000000000..965904a987855 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,npcm750-fiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Flash Interface Unit (FIU) SPI Controller + +maintainers: + - Tomer Maimon + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +description: | + NPCM FIU supports single, dual and quad communication interface. + + The NPCM7XX supports three FIU modules: + FIU0 and FIUx support two chip selects + FIU3 supports four chip selects. + + The NPCM8XX supports four FIU modules: + FIU0 and FIUx support two chip selects + FIU1 and FIU3 support four chip selects. + + The FIU control register block is always required. The direct-mapped + flash window is optional because the controller can still access flash + through the UMA path when that mapping is not described. + + Alias convention: + The '/aliases' node should define: + For NPCM7xx: fiu0=&fiu0; fiu1=&fiu3; fiu2=&fiux; + For NPCM8xx: fiu0=&fiu0; fiu1=&fiu3; fiu2=&fiux; fiu3=&fiu1; + +properties: + compatible: + enum: + - nuvoton,npcm750-fiu # Poleg NPCM7XX + - nuvoton,npcm845-fiu # Arbel NPCM8XX + + reg: + description: + The first resource is the FIU control register block. An optional second + resource describes the direct-mapped flash window used for direct + read/write accesses. + minItems: 1 + items: + - description: FIU control registers + - description: Memory-mapped flash contents + + reg-names: + description: + Resource names for the control registers and optional direct-mapped + flash window. + minItems: 1 + items: + - const: control + - const: memory + + clocks: + maxItems: 1 + description: FIU reference clock. + + nuvoton,spix-mode: + type: boolean + description: Enable SPIX mode for an expansion bus to an ASIC or CPLD. + +required: + - compatible + - reg + - reg-names + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + spi@fb000000 { + compatible = "nuvoton,npcm750-fiu"; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_SPI0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; + };