From: Greg Kroah-Hartman Date: Thu, 23 Apr 2026 09:01:14 +0000 (+0200) Subject: 6.18-stable patches X-Git-Url: http://git.ipfire.org/gitweb/?a=commitdiff_plain;h=478a1701523cf25ab053eec9e0bbf15719d90e3c;p=thirdparty%2Fkernel%2Fstable-queue.git 6.18-stable patches added patches: arm64-errata-work-around-early-cme-dvmsync-acknowledgement.patch arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-for-tlb-maintenance.patch arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s1ish.patch --- diff --git a/queue-6.18/arm64-cputype-add-c1-pro-definitions.patch b/queue-6.18/arm64-cputype-add-c1-pro-definitions.patch index af34240e92..392d711cc4 100644 --- a/queue-6.18/arm64-cputype-add-c1-pro-definitions.patch +++ b/queue-6.18/arm64-cputype-add-c1-pro-definitions.patch @@ -1,7 +1,10 @@ -From 66ca32af358c11a23108700529612bfd0206a44b Mon Sep 17 00:00:00 2001 -From: Sasha Levin +From stable+bounces-240113-greg=kroah.com@vger.kernel.org Tue Apr 21 12:02:38 2026 +From: Catalin Marinas Date: Tue, 21 Apr 2026 11:00:16 +0100 Subject: arm64: cputype: Add C1-Pro definitions +To: stable@vger.kernel.org +Cc: Will Deacon , linux-arm-kernel@lists.infradead.org +Message-ID: <20260421100018.335793-6-catalin.marinas@arm.com> From: Catalin Marinas @@ -20,13 +23,11 @@ Cc: Will Deacon Cc: James Morse Reviewed-by: Will Deacon Signed-off-by: Catalin Marinas -Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman --- - arch/arm64/include/asm/cputype.h | 2 ++ + arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h -index 9b00b75acbf29..18f98fb7ee783 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -98,6 +98,7 @@ @@ -45,6 +46,3 @@ index 9b00b75acbf29..18f98fb7ee783 100644 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) --- -2.53.0 - diff --git a/queue-6.18/arm64-errata-work-around-early-cme-dvmsync-acknowled.patch b/queue-6.18/arm64-errata-work-around-early-cme-dvmsync-acknowledgement.patch similarity index 80% rename from queue-6.18/arm64-errata-work-around-early-cme-dvmsync-acknowled.patch rename to queue-6.18/arm64-errata-work-around-early-cme-dvmsync-acknowledgement.patch index 4e1d54e4dd..c55e5b9131 100644 --- a/queue-6.18/arm64-errata-work-around-early-cme-dvmsync-acknowled.patch +++ b/queue-6.18/arm64-errata-work-around-early-cme-dvmsync-acknowledgement.patch @@ -1,7 +1,10 @@ -From faa8d2c214b68a6e5a2650041f3e05b0ce27b6a6 Mon Sep 17 00:00:00 2001 -From: Sasha Levin +From stable+bounces-240114-greg=kroah.com@vger.kernel.org Tue Apr 21 12:07:30 2026 +From: Catalin Marinas Date: Tue, 21 Apr 2026 11:00:17 +0100 Subject: arm64: errata: Work around early CME DVMSync acknowledgement +To: stable@vger.kernel.org +Cc: Will Deacon , linux-arm-kernel@lists.infradead.org +Message-ID: <20260421100018.335793-7-catalin.marinas@arm.com> From: Catalin Marinas @@ -28,23 +31,21 @@ Cc: James Morse Cc: Mark Brown Reviewed-by: Will Deacon Signed-off-by: Catalin Marinas -Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman --- - Documentation/arch/arm64/silicon-errata.rst | 2 + - arch/arm64/Kconfig | 12 ++++ - arch/arm64/include/asm/cpucaps.h | 2 + - arch/arm64/include/asm/fpsimd.h | 21 ++++++ - arch/arm64/include/asm/tlbbatch.h | 10 ++- - arch/arm64/include/asm/tlbflush.h | 72 ++++++++++++++++++- - arch/arm64/kernel/cpu_errata.c | 30 ++++++++ - arch/arm64/kernel/entry-common.c | 3 + - arch/arm64/kernel/fpsimd.c | 79 +++++++++++++++++++++ - arch/arm64/kernel/process.c | 36 ++++++++++ - arch/arm64/tools/cpucaps | 1 + + Documentation/arch/arm64/silicon-errata.rst | 2 + arch/arm64/Kconfig | 12 ++++ + arch/arm64/include/asm/cpucaps.h | 2 + arch/arm64/include/asm/fpsimd.h | 21 +++++++ + arch/arm64/include/asm/tlbbatch.h | 10 ++- + arch/arm64/include/asm/tlbflush.h | 72 ++++++++++++++++++++++++- + arch/arm64/kernel/cpu_errata.c | 30 ++++++++++ + arch/arm64/kernel/entry-common.c | 3 + + arch/arm64/kernel/fpsimd.c | 79 ++++++++++++++++++++++++++++ + arch/arm64/kernel/process.c | 36 ++++++++++++ + arch/arm64/tools/cpucaps | 1 11 files changed, 264 insertions(+), 4 deletions(-) -diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst -index a7ec57060f64f..93cdf16937159 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -202,6 +202,8 @@ stable kernels. @@ -56,8 +57,6 @@ index a7ec57060f64f..93cdf16937159 100644 | ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CPRE_ERRATA| | | | #562869,1047329 | | +----------------+-----------------+-----------------+-----------------------------+ -diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig -index 6663ffd23f252..840a945cb4acd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1154,6 +1154,18 @@ config ARM64_ERRATUM_3194386 @@ -79,11 +78,9 @@ index 6663ffd23f252..840a945cb4acd 100644 config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y -diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h -index 9d769291a3067..121210b7ffd0b 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h -@@ -66,6 +66,8 @@ cpucap_is_possible(const unsigned int cap) +@@ -66,6 +66,8 @@ cpucap_is_possible(const unsigned int ca return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI); case ARM64_WORKAROUND_SPECULATIVE_SSBS: return IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386); @@ -92,11 +89,9 @@ index 9d769291a3067..121210b7ffd0b 100644 case ARM64_MPAM: /* * KVM MPAM support doesn't rely on the host kernel supporting MPAM. -diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h -index b8cf0ea43cc05..0fa8d1d5722e0 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h -@@ -428,6 +428,24 @@ static inline size_t sme_state_size(struct task_struct const *task) +@@ -428,6 +428,24 @@ static inline size_t sme_state_size(stru return __sme_state_size(task_get_sme_vl(task)); } @@ -121,7 +116,7 @@ index b8cf0ea43cc05..0fa8d1d5722e0 100644 #else static inline void sme_user_disable(void) { BUILD_BUG(); } -@@ -456,6 +474,9 @@ static inline size_t sme_state_size(struct task_struct const *task) +@@ -456,6 +474,9 @@ static inline size_t sme_state_size(stru return 0; } @@ -131,8 +126,6 @@ index b8cf0ea43cc05..0fa8d1d5722e0 100644 #endif /* ! CONFIG_ARM64_SME */ /* For use by EFI runtime services calls only */ -diff --git a/arch/arm64/include/asm/tlbbatch.h b/arch/arm64/include/asm/tlbbatch.h -index fedb0b87b8db4..6297631532e59 100644 --- a/arch/arm64/include/asm/tlbbatch.h +++ b/arch/arm64/include/asm/tlbbatch.h @@ -2,11 +2,17 @@ @@ -155,11 +148,9 @@ index fedb0b87b8db4..6297631532e59 100644 }; #endif /* _ARCH_ARM64_TLBBATCH_H */ -diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h -index ba36e91aefb82..f53ab3ba0c48b 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h -@@ -80,6 +80,71 @@ static inline unsigned long get_trans_granule(void) +@@ -80,6 +80,71 @@ static inline unsigned long get_trans_gr } } @@ -231,7 +222,7 @@ index ba36e91aefb82..f53ab3ba0c48b 100644 /* * Level-based TLBI operations. * -@@ -189,12 +254,14 @@ static inline void __tlbi_sync_s1ish(struct mm_struct *mm) +@@ -189,12 +254,14 @@ static inline void __tlbi_sync_s1ish(str { dsb(ish); __repeat_tlbi_sync(vale1is, 0); @@ -247,7 +238,7 @@ index ba36e91aefb82..f53ab3ba0c48b 100644 } static inline void __tlbi_sync_s1ish_kernel(void) -@@ -357,7 +424,7 @@ static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) +@@ -357,7 +424,7 @@ static inline bool arch_tlbbatch_should_ */ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { @@ -256,7 +247,7 @@ index ba36e91aefb82..f53ab3ba0c48b 100644 } /* -@@ -546,6 +613,7 @@ static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b +@@ -546,6 +613,7 @@ static inline void arch_tlbbatch_add_pen struct mm_struct *mm, unsigned long start, unsigned long end) { __flush_tlb_range_nosync(mm, start, end, PAGE_SIZE, true, 3); @@ -264,8 +255,6 @@ index ba36e91aefb82..f53ab3ba0c48b 100644 } #endif -diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c -index 8cb3b575a0316..6c8c4301d9c6d 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -11,6 +11,7 @@ @@ -276,7 +265,7 @@ index 8cb3b575a0316..6c8c4301d9c6d 100644 #include #include -@@ -551,6 +552,23 @@ static const struct midr_range erratum_spec_ssbs_list[] = { +@@ -551,6 +552,23 @@ static const struct midr_range erratum_s }; #endif @@ -300,7 +289,7 @@ index 8cb3b575a0316..6c8c4301d9c6d 100644 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 static const struct midr_range erratum_ac03_cpu_38_list[] = { MIDR_ALL_VERSIONS(MIDR_AMPERE1), -@@ -870,6 +888,18 @@ const struct arm64_cpu_capabilities arm64_errata[] = { +@@ -870,6 +888,18 @@ const struct arm64_cpu_capabilities arm6 ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), }, #endif @@ -319,8 +308,6 @@ index 8cb3b575a0316..6c8c4301d9c6d 100644 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD { .desc = "ARM errata 2966298, 3117295", -diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c -index a9c81715ce59e..5b97dfcf796d9 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -21,6 +21,7 @@ @@ -331,7 +318,7 @@ index a9c81715ce59e..5b97dfcf796d9 100644 #include #include #include -@@ -84,6 +85,7 @@ static __always_inline void __enter_from_user_mode(struct pt_regs *regs) +@@ -84,6 +85,7 @@ static __always_inline void __enter_from { enter_from_user_mode(regs); mte_disable_tco_entry(current); @@ -339,7 +326,7 @@ index a9c81715ce59e..5b97dfcf796d9 100644 } static __always_inline void arm64_enter_from_user_mode(struct pt_regs *regs) -@@ -102,6 +104,7 @@ static __always_inline void arm64_exit_to_user_mode(struct pt_regs *regs) +@@ -102,6 +104,7 @@ static __always_inline void arm64_exit_t local_irq_disable(); exit_to_user_mode_prepare(regs); local_daif_mask(); @@ -347,8 +334,6 @@ index a9c81715ce59e..5b97dfcf796d9 100644 mte_check_tfsr_exit(); exit_to_user_mode(); } -diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c -index e3f8f51748bc9..ca18214ce2abe 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -15,6 +15,7 @@ @@ -367,7 +352,7 @@ index e3f8f51748bc9..ca18214ce2abe 100644 #include #include #include -@@ -1384,6 +1386,83 @@ void do_sve_acc(unsigned long esr, struct pt_regs *regs) +@@ -1384,6 +1386,83 @@ void do_sve_acc(unsigned long esr, struc put_cpu_fpsimd_context(); } @@ -451,8 +436,6 @@ index e3f8f51748bc9..ca18214ce2abe 100644 /* * Trapped SME access * -diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c -index 489554931231e..4c328b7c79ba3 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -26,6 +26,7 @@ @@ -505,7 +488,7 @@ index 489554931231e..4c328b7c79ba3 100644 fpsimd_release_task(tsk); } -@@ -356,6 +390,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) +@@ -356,6 +390,8 @@ int arch_dup_task_struct(struct task_str *dst = *src; @@ -514,8 +497,6 @@ index 489554931231e..4c328b7c79ba3 100644 /* * Drop stale reference to src's sve_state and convert dst to * non-streaming FPSIMD mode. -diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps -index 1b32c1232d28d..16d123088ddd4 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -101,6 +101,7 @@ WORKAROUND_2077057 @@ -526,6 +507,3 @@ index 1b32c1232d28d..16d123088ddd4 100644 WORKAROUND_AMPERE_AC03_CPU_38 WORKAROUND_AMPERE_AC04_CPU_23 WORKAROUND_TRBE_OVERWRITE_FILL_MODE --- -2.53.0 - diff --git a/queue-6.18/arm64-tlb-allow-xzr-argument-to-tlbi-ops.patch b/queue-6.18/arm64-tlb-allow-xzr-argument-to-tlbi-ops.patch index 2119462a07..052fd8b629 100644 --- a/queue-6.18/arm64-tlb-allow-xzr-argument-to-tlbi-ops.patch +++ b/queue-6.18/arm64-tlb-allow-xzr-argument-to-tlbi-ops.patch @@ -1,7 +1,10 @@ -From bd04b0c2c4878edbfe8b4fad3e198ce637d1be4f Mon Sep 17 00:00:00 2001 -From: Sasha Levin +From stable+bounces-240109-greg=kroah.com@vger.kernel.org Tue Apr 21 12:02:28 2026 +From: Catalin Marinas Date: Tue, 21 Apr 2026 11:00:12 +0100 Subject: arm64: tlb: Allow XZR argument to TLBI ops +To: stable@vger.kernel.org +Cc: Will Deacon , linux-arm-kernel@lists.infradead.org +Message-ID: <20260421100018.335793-2-catalin.marinas@arm.com> From: Mark Rutland @@ -29,13 +32,11 @@ Cc: Ryan Roberts Cc: Will Deacon Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas -Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman --- - arch/arm64/include/asm/tlbflush.h | 6 +++--- + arch/arm64/include/asm/tlbflush.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h -index 18a5dc0c9a540..0ddb344f83b4e 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -38,12 +38,12 @@ @@ -54,6 +55,3 @@ index 18a5dc0c9a540..0ddb344f83b4e 100644 #define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg) --- -2.53.0 - diff --git a/queue-6.18/arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-.patch b/queue-6.18/arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-for-tlb-maintenance.patch similarity index 73% rename from queue-6.18/arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-.patch rename to queue-6.18/arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-for-tlb-maintenance.patch index 2636567a3c..f928354cd8 100644 --- a/queue-6.18/arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-.patch +++ b/queue-6.18/arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-for-tlb-maintenance.patch @@ -1,8 +1,10 @@ -From b0133a902703b93dd46ef288b1f91ca5a126cd20 Mon Sep 17 00:00:00 2001 -From: Sasha Levin +From stable+bounces-240111-greg=kroah.com@vger.kernel.org Tue Apr 21 12:07:14 2026 +From: Catalin Marinas Date: Tue, 21 Apr 2026 11:00:14 +0100 -Subject: arm64: tlb: Introduce __tlbi_sync_s1ish_{kernel,batch}() for TLB - maintenance +Subject: arm64: tlb: Introduce __tlbi_sync_s1ish_{kernel,batch}() for TLB maintenance +To: stable@vger.kernel.org +Cc: Will Deacon , linux-arm-kernel@lists.infradead.org +Message-ID: <20260421100018.335793-4-catalin.marinas@arm.com> From: Catalin Marinas @@ -22,16 +24,14 @@ Acked-by: Mark Rutland Cc: Will Deacon Reviewed-by: Will Deacon Signed-off-by: Catalin Marinas -Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman --- - arch/arm64/include/asm/tlbflush.h | 20 ++++++++++++++++---- + arch/arm64/include/asm/tlbflush.h | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) -diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h -index c87d13bee37de..387bd86af7021 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h -@@ -191,6 +191,18 @@ static inline void __tlbi_sync_s1ish(void) +@@ -191,6 +191,18 @@ static inline void __tlbi_sync_s1ish(voi __repeat_tlbi_sync(vale1is, 0); } @@ -59,7 +59,7 @@ index c87d13bee37de..387bd86af7021 100644 isb(); } -@@ -345,7 +357,7 @@ static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) +@@ -345,7 +357,7 @@ static inline bool arch_tlbbatch_should_ */ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { @@ -68,7 +68,7 @@ index c87d13bee37de..387bd86af7021 100644 } /* -@@ -512,7 +524,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end +@@ -512,7 +524,7 @@ static inline void flush_tlb_kernel_rang dsb(ishst); __flush_tlb_range_op(vaale1is, start, pages, stride, 0, TLBI_TTL_UNKNOWN, false, lpa2_is_enabled()); @@ -77,7 +77,7 @@ index c87d13bee37de..387bd86af7021 100644 isb(); } -@@ -526,7 +538,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) +@@ -526,7 +538,7 @@ static inline void __flush_tlb_kernel_pg dsb(ishst); __tlbi(vaae1is, addr); @@ -86,6 +86,3 @@ index c87d13bee37de..387bd86af7021 100644 isb(); } --- -2.53.0 - diff --git a/queue-6.18/arm64-tlb-optimize-arm64_workaround_repeat_tlbi.patch b/queue-6.18/arm64-tlb-optimize-arm64_workaround_repeat_tlbi.patch index bb305e32ce..856ef09602 100644 --- a/queue-6.18/arm64-tlb-optimize-arm64_workaround_repeat_tlbi.patch +++ b/queue-6.18/arm64-tlb-optimize-arm64_workaround_repeat_tlbi.patch @@ -1,7 +1,10 @@ -From ff4dc5561fb57e82c7d972a1faa44d736aba839b Mon Sep 17 00:00:00 2001 -From: Sasha Levin +From stable+bounces-240110-greg=kroah.com@vger.kernel.org Tue Apr 21 12:02:29 2026 +From: Catalin Marinas Date: Tue, 21 Apr 2026 11:00:13 +0100 Subject: arm64: tlb: Optimize ARM64_WORKAROUND_REPEAT_TLBI +To: stable@vger.kernel.org +Cc: Will Deacon , linux-arm-kernel@lists.infradead.org +Message-ID: <20260421100018.335793-3-catalin.marinas@arm.com> From: Mark Rutland @@ -178,18 +181,16 @@ Cc: Ryan Roberts Cc: Will Deacon Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas -Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman --- - arch/arm64/include/asm/tlbflush.h | 59 ++++++++++++++++++------------- - arch/arm64/kernel/sys_compat.c | 2 +- - arch/arm64/kvm/hyp/nvhe/mm.c | 2 +- - arch/arm64/kvm/hyp/nvhe/tlb.c | 8 ++--- - arch/arm64/kvm/hyp/pgtable.c | 2 +- - arch/arm64/kvm/hyp/vhe/tlb.c | 10 +++--- + arch/arm64/include/asm/tlbflush.h | 59 ++++++++++++++++++++++---------------- + arch/arm64/kernel/sys_compat.c | 2 - + arch/arm64/kvm/hyp/nvhe/mm.c | 2 - + arch/arm64/kvm/hyp/nvhe/tlb.c | 8 ++--- + arch/arm64/kvm/hyp/pgtable.c | 2 - + arch/arm64/kvm/hyp/vhe/tlb.c | 10 +++--- 6 files changed, 47 insertions(+), 36 deletions(-) -diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h -index 0ddb344f83b4e..c87d13bee37de 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -31,18 +31,10 @@ @@ -211,7 +212,7 @@ index 0ddb344f83b4e..c87d13bee37de 100644 : : "rZ" (arg)) #define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg) -@@ -181,6 +173,34 @@ static inline unsigned long get_trans_granule(void) +@@ -181,6 +173,34 @@ static inline unsigned long get_trans_gr (__pages >> (5 * (scale) + 1)) - 1; \ }) @@ -255,7 +256,7 @@ index 0ddb344f83b4e..c87d13bee37de 100644 isb(); } -@@ -278,7 +298,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm) +@@ -278,7 +298,7 @@ static inline void flush_tlb_mm(struct m asid = __TLBI_VADDR(0, ASID(mm)); __tlbi(aside1is, asid); __tlbi_user(aside1is, asid); @@ -264,7 +265,7 @@ index 0ddb344f83b4e..c87d13bee37de 100644 mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); } -@@ -305,20 +325,11 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, +@@ -305,20 +325,11 @@ static inline void flush_tlb_page(struct unsigned long uaddr) { flush_tlb_page_nosync(vma, uaddr); @@ -286,7 +287,7 @@ index 0ddb344f83b4e..c87d13bee37de 100644 return true; } -@@ -334,7 +345,7 @@ static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) +@@ -334,7 +345,7 @@ static inline bool arch_tlbbatch_should_ */ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { @@ -295,7 +296,7 @@ index 0ddb344f83b4e..c87d13bee37de 100644 } /* -@@ -469,7 +480,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, +@@ -469,7 +480,7 @@ static inline void __flush_tlb_range(str { __flush_tlb_range_nosync(vma->vm_mm, start, end, stride, last_level, tlb_level); @@ -304,7 +305,7 @@ index 0ddb344f83b4e..c87d13bee37de 100644 } static inline void flush_tlb_range(struct vm_area_struct *vma, -@@ -501,7 +512,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end +@@ -501,7 +512,7 @@ static inline void flush_tlb_kernel_rang dsb(ishst); __flush_tlb_range_op(vaale1is, start, pages, stride, 0, TLBI_TTL_UNKNOWN, false, lpa2_is_enabled()); @@ -313,7 +314,7 @@ index 0ddb344f83b4e..c87d13bee37de 100644 isb(); } -@@ -515,7 +526,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) +@@ -515,7 +526,7 @@ static inline void __flush_tlb_kernel_pg dsb(ishst); __tlbi(vaae1is, addr); @@ -322,11 +323,9 @@ index 0ddb344f83b4e..c87d13bee37de 100644 isb(); } -diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c -index 4a609e9b65de0..b9d4998c97efa 100644 --- a/arch/arm64/kernel/sys_compat.c +++ b/arch/arm64/kernel/sys_compat.c -@@ -37,7 +37,7 @@ __do_compat_cache_op(unsigned long start, unsigned long end) +@@ -37,7 +37,7 @@ __do_compat_cache_op(unsigned long start * We pick the reserved-ASID to minimise the impact. */ __tlbi(aside1is, __TLBI_VADDR(0, 0)); @@ -335,11 +334,9 @@ index 4a609e9b65de0..b9d4998c97efa 100644 } ret = caches_clean_inval_user_pou(start, start + chunk); -diff --git a/arch/arm64/kvm/hyp/nvhe/mm.c b/arch/arm64/kvm/hyp/nvhe/mm.c -index ae8391baebc30..218976287d3fe 100644 --- a/arch/arm64/kvm/hyp/nvhe/mm.c +++ b/arch/arm64/kvm/hyp/nvhe/mm.c -@@ -271,7 +271,7 @@ static void fixmap_clear_slot(struct hyp_fixmap_slot *slot) +@@ -271,7 +271,7 @@ static void fixmap_clear_slot(struct hyp */ dsb(ishst); __tlbi_level(vale2is, __TLBI_VADDR(addr, 0), level); @@ -348,11 +345,9 @@ index ae8391baebc30..218976287d3fe 100644 isb(); } -diff --git a/arch/arm64/kvm/hyp/nvhe/tlb.c b/arch/arm64/kvm/hyp/nvhe/tlb.c -index 48da9ca9763f6..3dc1ce0d27fe6 100644 --- a/arch/arm64/kvm/hyp/nvhe/tlb.c +++ b/arch/arm64/kvm/hyp/nvhe/tlb.c -@@ -169,7 +169,7 @@ void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, +@@ -169,7 +169,7 @@ void __kvm_tlb_flush_vmid_ipa(struct kvm */ dsb(ish); __tlbi(vmalle1is); @@ -361,7 +356,7 @@ index 48da9ca9763f6..3dc1ce0d27fe6 100644 isb(); exit_vmid_context(&cxt); -@@ -226,7 +226,7 @@ void __kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu, +@@ -226,7 +226,7 @@ void __kvm_tlb_flush_vmid_range(struct k dsb(ish); __tlbi(vmalle1is); @@ -370,7 +365,7 @@ index 48da9ca9763f6..3dc1ce0d27fe6 100644 isb(); exit_vmid_context(&cxt); -@@ -240,7 +240,7 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu) +@@ -240,7 +240,7 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_ enter_vmid_context(mmu, &cxt, false); __tlbi(vmalls12e1is); @@ -386,11 +381,9 @@ index 48da9ca9763f6..3dc1ce0d27fe6 100644 - dsb(ish); + __tlbi_sync_s1ish_hyp(); } -diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c -index c351b4abd5dbf..cbf8cd2e16735 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c -@@ -483,7 +483,7 @@ static int hyp_unmap_walker(const struct kvm_pgtable_visit_ctx *ctx, +@@ -483,7 +483,7 @@ static int hyp_unmap_walker(const struct *unmapped += granule; } @@ -399,11 +392,9 @@ index c351b4abd5dbf..cbf8cd2e16735 100644 isb(); mm_ops->put_page(ctx->ptep); -diff --git a/arch/arm64/kvm/hyp/vhe/tlb.c b/arch/arm64/kvm/hyp/vhe/tlb.c -index ec25698186297..35855dadfb1b3 100644 --- a/arch/arm64/kvm/hyp/vhe/tlb.c +++ b/arch/arm64/kvm/hyp/vhe/tlb.c -@@ -115,7 +115,7 @@ void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, +@@ -115,7 +115,7 @@ void __kvm_tlb_flush_vmid_ipa(struct kvm */ dsb(ish); __tlbi(vmalle1is); @@ -412,7 +403,7 @@ index ec25698186297..35855dadfb1b3 100644 isb(); exit_vmid_context(&cxt); -@@ -176,7 +176,7 @@ void __kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu, +@@ -176,7 +176,7 @@ void __kvm_tlb_flush_vmid_range(struct k dsb(ish); __tlbi(vmalle1is); @@ -421,7 +412,7 @@ index ec25698186297..35855dadfb1b3 100644 isb(); exit_vmid_context(&cxt); -@@ -192,7 +192,7 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu) +@@ -192,7 +192,7 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_ enter_vmid_context(mmu, &cxt); __tlbi(vmalls12e1is); @@ -439,7 +430,7 @@ index ec25698186297..35855dadfb1b3 100644 } /* -@@ -358,7 +358,7 @@ int __kvm_tlbi_s1e2(struct kvm_s2_mmu *mmu, u64 va, u64 sys_encoding) +@@ -358,7 +358,7 @@ int __kvm_tlbi_s1e2(struct kvm_s2_mmu *m default: ret = -EINVAL; } @@ -448,6 +439,3 @@ index ec25698186297..35855dadfb1b3 100644 isb(); if (mmu) --- -2.53.0 - diff --git a/queue-6.18/arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s.patch b/queue-6.18/arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s1ish.patch similarity index 69% rename from queue-6.18/arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s.patch rename to queue-6.18/arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s1ish.patch index ac727e4ec4..b7106a145b 100644 --- a/queue-6.18/arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s.patch +++ b/queue-6.18/arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s1ish.patch @@ -1,7 +1,10 @@ -From 4f8d2ea4fb246a4a5b379779f9bdef1190582b1e Mon Sep 17 00:00:00 2001 -From: Sasha Levin +From stable+bounces-240112-greg=kroah.com@vger.kernel.org Tue Apr 21 12:02:34 2026 +From: Catalin Marinas Date: Tue, 21 Apr 2026 11:00:15 +0100 Subject: arm64: tlb: Pass the corresponding mm to __tlbi_sync_s1ish() +To: stable@vger.kernel.org +Cc: Will Deacon , linux-arm-kernel@lists.infradead.org +Message-ID: <20260421100018.335793-5-catalin.marinas@arm.com> From: Catalin Marinas @@ -14,14 +17,12 @@ Acked-by: Mark Rutland Cc: Will Deacon Reviewed-by: Will Deacon Signed-off-by: Catalin Marinas -Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman --- - arch/arm64/include/asm/tlbflush.h | 8 ++++---- - arch/arm64/kernel/sys_compat.c | 2 +- + arch/arm64/include/asm/tlbflush.h | 8 ++++---- + arch/arm64/kernel/sys_compat.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) -diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h -index 387bd86af7021..ba36e91aefb82 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -185,7 +185,7 @@ do { \ @@ -33,7 +34,7 @@ index 387bd86af7021..ba36e91aefb82 100644 { dsb(ish); __repeat_tlbi_sync(vale1is, 0); -@@ -310,7 +310,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm) +@@ -310,7 +310,7 @@ static inline void flush_tlb_mm(struct m asid = __TLBI_VADDR(0, ASID(mm)); __tlbi(aside1is, asid); __tlbi_user(aside1is, asid); @@ -42,7 +43,7 @@ index 387bd86af7021..ba36e91aefb82 100644 mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); } -@@ -337,7 +337,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, +@@ -337,7 +337,7 @@ static inline void flush_tlb_page(struct unsigned long uaddr) { flush_tlb_page_nosync(vma, uaddr); @@ -51,7 +52,7 @@ index 387bd86af7021..ba36e91aefb82 100644 } static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) -@@ -492,7 +492,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, +@@ -492,7 +492,7 @@ static inline void __flush_tlb_range(str { __flush_tlb_range_nosync(vma->vm_mm, start, end, stride, last_level, tlb_level); @@ -60,11 +61,9 @@ index 387bd86af7021..ba36e91aefb82 100644 } static inline void flush_tlb_range(struct vm_area_struct *vma, -diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c -index b9d4998c97efa..03fde2677d5be 100644 --- a/arch/arm64/kernel/sys_compat.c +++ b/arch/arm64/kernel/sys_compat.c -@@ -37,7 +37,7 @@ __do_compat_cache_op(unsigned long start, unsigned long end) +@@ -37,7 +37,7 @@ __do_compat_cache_op(unsigned long start * We pick the reserved-ASID to minimise the impact. */ __tlbi(aside1is, __TLBI_VADDR(0, 0)); @@ -73,6 +72,3 @@ index b9d4998c97efa..03fde2677d5be 100644 } ret = caches_clean_inval_user_pou(start, start + chunk); --- -2.53.0 - diff --git a/queue-6.18/series b/queue-6.18/series index 0b6a08e962..debd49f279 100644 --- a/queue-6.18/series +++ b/queue-6.18/series @@ -1,10 +1,4 @@ crypto-authencesn-fix-src-offset-when-decrypting-in-place.patch -arm64-tlb-allow-xzr-argument-to-tlbi-ops.patch -arm64-tlb-optimize-arm64_workaround_repeat_tlbi.patch -arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-.patch -arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s.patch -arm64-cputype-add-c1-pro-definitions.patch -arm64-errata-work-around-early-cme-dvmsync-acknowled.patch ipv6-add-null-checks-for-idev-in-srv6-paths.patch net-ethernet-mtk_eth_soc-initialize-ppe-per-tag-laye.patch drm-amdgpu-replace-pasid-idr-with-xarray.patch @@ -13,3 +7,9 @@ crypto-krb5enc-fix-async-decrypt-skipping-hash-verification.patch scripts-generate_rust_analyzer.py-define-scripts.patch ksmbd-fix-use-after-free-in-__ksmbd_close_fd-via-durable-scavenger.patch ksmbd-validate-owner-of-durable-handle-on-reconnect.patch +arm64-tlb-allow-xzr-argument-to-tlbi-ops.patch +arm64-tlb-optimize-arm64_workaround_repeat_tlbi.patch +arm64-tlb-introduce-__tlbi_sync_s1ish_-kernel-batch-for-tlb-maintenance.patch +arm64-tlb-pass-the-corresponding-mm-to-__tlbi_sync_s1ish.patch +arm64-cputype-add-c1-pro-definitions.patch +arm64-errata-work-around-early-cme-dvmsync-acknowledgement.patch