From: Tianyang Zhang Date: Wed, 13 May 2026 01:28:32 +0000 (+0800) Subject: Docs/LoongArch: Add advanced extended IRQ model X-Git-Url: http://git.ipfire.org/gitweb/?a=commitdiff_plain;h=89bb21e9b57defa9a33ff01020d44f3fd6802026;p=thirdparty%2Fkernel%2Flinux.git Docs/LoongArch: Add advanced extended IRQ model Introduce a new advanced extended interrupt model with redirect interrupt controllers. When the redirect interrupt controller is enabled, the routing target of MSI interrupts is no longer a specific CPU and vector number, but a specific redirect entry. The actual CPU and vector number used are described by the redirect entry. Signed-off-by: Tianyang Zhang Signed-off-by: Thomas Gleixner Acked-by: Huacai Chen Link: https://patch.msgid.link/20260513012839.2856463-2-zhangtianyang@loongson.cn --- diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst index 8f5c3345109e6..774d40dc6a7ee 100644 --- a/Documentation/arch/loongarch/irq-chip-model.rst +++ b/Documentation/arch/loongarch/irq-chip-model.rst @@ -181,6 +181,41 @@ go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly:: | Devices | +---------+ +Advanced Extended IRQ model (with redirection) +============================================== + +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go +to REDIRECT for remapping it to AVECINTC, and then go to CPUINTC directly, while +all other devices interrupts go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and +then go to CPUINTC directly:: + + +-----+ +-----------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +-----------------------+ +-------+ + ^ ^ ^ + | | | + | +----------+ | + +---------+ | AVECINTC | +---------+ +-------+ + | EIOINTC | +----------+ | LIOINTC | <-- | UARTs | + +---------+ | REDIRECT | +---------+ +-------+ + ^ +----------+ + | ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPI-related definitions ======================== diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst index d4ff80de47b63..87b58aee92e1d 100644 --- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst +++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst @@ -174,6 +174,40 @@ CPU串口(UARTs)中断发送到LIOINTC,PCH-MSI中断发送到AVECINTC, | Devices | +---------+ +高级扩展IRQ模型 (带重定向) +========================== + +在这种模型里面,IPI(Inter-Processor Interrupt)和CPU本地时钟中断直接发送到CPUINTC, +CPU串口(UARTs)中断发送到LIOINTC,PCH-MSI中断首先发送到REDIRECT模块,完成重定向后发 +送到AVECINTC,而后通过AVECINTC直接送达CPUINTC,而其他所有设备的中断则分别发送到所连 +接的PCH-PIC/PCH-LPC,然后由EIOINTC统一收集,再直接到达CPUINTC:: + + +-----+ +-----------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +-----------------------+ +-------+ + ^ ^ ^ + | | | + | +----------+ | + +---------+ | AVECINTC | +---------+ +-------+ + | EIOINTC | +----------+ | LIOINTC | <-- | UARTs | + +---------+ | REDIRECT | +---------+ +-------+ + ^ +----------+ + | ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPI相关的定义 ==============