From: Balaji Selvanathan Date: Wed, 3 Dec 2025 11:07:30 +0000 (+0530) Subject: drivers: clk: qcom: sc7280: Add USB3 PHY pipe clock X-Git-Tag: v2026.07-rc1~8^2~24 X-Git-Url: http://git.ipfire.org/gitweb/?a=commitdiff_plain;h=c808ab5fed990e2aa8e4ca6a855db49a225edd64;p=thirdparty%2Fu-boot.git drivers: clk: qcom: sc7280: Add USB3 PHY pipe clock Add support for GCC_USB3_PRIM_PHY_PIPE_CLK which is required by the USB3 PHY on SC7280/QCM6490 platforms. Signed-off-by: Balaji Selvanathan Reviewed-by: Neil Armstrong Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20251203110735.1959862-2-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly --- diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 7b6ed826023..403995e5a0a 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -116,6 +116,7 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1), GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1), GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf05c, 1), GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1), GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1), GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),