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2 months agodrm/amd/pm: Add smu v15_0_8 message header
Hawking Zhang [Sun, 2 Nov 2025 10:56:52 +0000 (18:56 +0800)] 
drm/amd/pm: Add smu v15_0_8 message header

Add smu v15_0_8 message header

v2: squash in updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/pm: Add smu v15_0_8 driver interface header
Hawking Zhang [Sun, 2 Nov 2025 10:55:16 +0000 (18:55 +0800)] 
drm/amd/pm: Add smu v15_0_8 driver interface header

Add smu v15_0_8 driver interface header

v2: squash in updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: make amdgpu_user_wait_ioctl more resilent v2
Christian König [Thu, 29 Jan 2026 11:58:10 +0000 (12:58 +0100)] 
drm/amdgpu: make amdgpu_user_wait_ioctl more resilent v2

When the memory allocated by userspace isn't sufficient for all the
fences then just wait on them instead of returning an error.

v2: use correct variable as pointed out by Sunil

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: replace WARN with DRM_ERROR for invalid sched priority
Jesse.Zhang [Fri, 13 Mar 2026 06:17:10 +0000 (14:17 +0800)] 
drm/amdgpu: replace WARN with DRM_ERROR for invalid sched priority

amdgpu_sched_ioctl() currently uses WARN(1, ...) when userspace passes
an out-of-range context priority value. WARN(1, ...) is unconditional
and produces a full stack trace, which is disproportionate for a simple
input validation failure -- the invalid value is already rejected with
-EINVAL on the next line.

Replace WARN(1, ...) with DRM_ERROR() to log the invalid value at an
appropriate level without generating a stack dump. The -EINVAL return
to userspace is unchanged.

No functional change for well-formed userspace callers.

v2:
- Reworked commit message to focus on appropriate log level for
  parameter validation
- Clarified that -EINVAL behavior is preserved (Vitaly)

v3: completely drop that warning.
   Invalid parameters should never clutter the system log. (Christian)

Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agoMerge tag 'amd-drm-next-7.1-2026-03-19' of https://gitlab.freedesktop.org/agd5f/linux...
Dave Airlie [Fri, 20 Mar 2026 16:21:54 +0000 (02:21 +1000)] 
Merge tag 'amd-drm-next-7.1-2026-03-19' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-7.1-2026-03-19:

amdgpu:
- Fix gamma 2.2 colorop TFs
- BO list fix
- LTO fix
- DC FP fix
- DisplayID handling fix
- DCN 2.01 fix
- MMHUB boundary fixes
- ISP fix
- TLB fence fix
- Hainan pm fix
- UserQ fixes
- MES 12.1 Updates
- GC 12.1 updates
- RAS fixes
- DML updates
- Cursor fixes
- SWSMU cleanups
- Misc cleanups
- Clean up duplicate format modifiers
- Devcoredump updates
- Cleanup mmhub cid handling
- Initial VCN 5.0.2 support
- Initial JPEG 5.0.2 support
- PSP 13.0.15 updates

amdkfd:
- Queue properties fix
- GC 12.1 updates

radeon:
- Hainan pm fix

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260319173334.479766-1-alexander.deucher@amd.com
2 months agodrm/amdgpu: Add client ids for gmcv9 mmhubs
Lijo Lazar [Tue, 17 Mar 2026 11:08:00 +0000 (16:38 +0530)] 
drm/amdgpu: Add client ids for gmcv9 mmhubs

Initialize client ids for gmcv9 mmhubs

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add client ids for mmhub v2.x
Lijo Lazar [Tue, 17 Mar 2026 08:09:56 +0000 (13:39 +0530)] 
drm/amdgpu: Add client ids for mmhub v2.x

Initialize client ids for mmhub v2.x

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add client ids for mmhub v3.x
Lijo Lazar [Tue, 17 Mar 2026 07:52:05 +0000 (13:22 +0530)] 
drm/amdgpu: Add client ids for mmhub v3.x

Initialize client ids for mmhub v3.x

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add client ids for mmhub v4.x
Lijo Lazar [Tue, 17 Mar 2026 07:41:18 +0000 (13:11 +0530)] 
drm/amdgpu: Add client ids for mmhub v4.x

Initialize client ids for mmhub v4.x

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add client id helpers to mmhub
Lijo Lazar [Tue, 17 Mar 2026 07:33:53 +0000 (13:03 +0530)] 
drm/amdgpu: Add client id helpers to mmhub

Add data structure and helpers to get client id data of mmhub.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agoRevert "drm/amd/display: Add NV12/P010 formats to primary plane"
Harry Wentland [Tue, 17 Mar 2026 17:04:51 +0000 (13:04 -0400)] 
Revert "drm/amd/display: Add NV12/P010 formats to primary plane"

With this change we're adding NV12 and P010 twice to reported
formats on a primary plane, which causes us to hit an assert
in Weston.

This reverts commit 63fff551318f5e0814b94f709a6dfaec789dcd7a.

Fixes: 63fff551318f ("drm/amd/display: Add NV12/P010 formats to primary plane")
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Remove dead negative offset check in amdgpu_virt_init_critical_region()
Srinivasan Shanmugam [Thu, 12 Mar 2026 13:23:59 +0000 (18:53 +0530)] 
drm/amdgpu: Remove dead negative offset check in amdgpu_virt_init_critical_region()

amdgpu_virt_init_critical_region() stores init_hdr_offset as u64.
The subsequent check for init_hdr_offset < 0 is therefore always false.

Drop the unreachable validation and rely on the existing
check_add_overflow() and VRAM end bounds check for offset validation.

This resolves the Smatch warning about comparing an unsigned value
against zero.

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:953 amdgpu_virt_init_critical_region() warn: unsigned 'init_hdr_offset' is never less than zero.

Fixes: 07009df6494d ("drm/amdgpu: Introduce SRIOV critical regions v2 during VF init")
Cc: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Ellen Pan <yunru.pan@amd.com>
Cc: Lijo Lazar <lijo.lazar@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Bokun Zhang <bokun.zhang@amd.com>
Reviewed-by: Ellen Pan <yunru.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Move amdgpu_vm_is_bo_always_valid() before first use
Srinivasan Shanmugam [Thu, 12 Mar 2026 15:04:48 +0000 (20:34 +0530)] 
drm/amdgpu: Move amdgpu_vm_is_bo_always_valid() before first use

Smatch reports that 'bo' could be NULL in amdgpu_vm_bo_update(), even
though amdgpu_vm_is_bo_always_valid() already checks for a NULL BO.

Move amdgpu_vm_is_bo_always_valid() earlier in the file so the helper
definition appears before its first use. This allows static analysis
tools to see the NULL check performed by the helper and avoids the
warning.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Drop redundant queue NULL check in hang detect worker
Srinivasan Shanmugam [Sun, 15 Mar 2026 07:12:42 +0000 (12:42 +0530)] 
drm/amdgpu: Drop redundant queue NULL check in hang detect worker

amdgpu_userq_hang_detect_work() retrieves the queue pointer using
container_of() from the embedded work item.

Since the work structure is part of struct amdgpu_usermode_queue,
the returned queue pointer cannot be NULL in normal execution.

Remove the redundant !queue check and keep the validation for
queue->userq_mgr.

Fixes the below:
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c:159 amdgpu_userq_hang_detect_work() warn: can 'queue' even be NULL?

Fixes: 290f46cf5726 ("drm/amdgpu: Implement user queue reset functionality")
Cc: Jesse Zhang <Jesse.Zhang@amd.com>
Cc: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Acked-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu : Update psp 13_0_15 ip block support
Mangesh Gadre [Sun, 1 Mar 2026 15:19:13 +0000 (15:19 +0000)] 
drm/amdgpu : Update psp 13_0_15 ip block support

Included psp_13_0_15 ip block for RAS

Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: rework amdgpu_userq_wait_ioctl v4
Christian König [Thu, 29 Jan 2026 11:29:26 +0000 (12:29 +0100)] 
drm/amdgpu: rework amdgpu_userq_wait_ioctl v4

Lockdep was complaining about a number of issues here. Especially lock
inversion between syncobj, dma_resv and copying things into userspace.

Rework the functionality. Split it up into multiple functions,
consistenly use memdup_array_user(), fix the lock inversions and a few
more bugs in error handling.

v2: drop the dma_fence leak fix, turned out that was actually correct,
    just not well documented. Apply some more cleanup suggestion from
    Tvrtko.
v3: rebase on already done cleanups
v4: add missing dma_fence_put() in error path.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: fix adding eviction fence
Christian König [Wed, 28 Jan 2026 15:07:03 +0000 (16:07 +0100)] 
drm/amdgpu: fix adding eviction fence

We can't add the eviction fence without validating the BO.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: fix eviction fence and userq manager shutdown
Christian König [Fri, 30 Jan 2026 15:46:36 +0000 (16:46 +0100)] 
drm/amdgpu: fix eviction fence and userq manager shutdown

That is a really complicated dance and wasn't implemented fully correct.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: completely rework eviction fence handling v2
Christian König [Wed, 28 Jan 2026 12:58:14 +0000 (13:58 +0100)] 
drm/amdgpu: completely rework eviction fence handling v2

Well that was broken on multiple levels.

First of all a lot of checks were placed at incorrect locations, especially if
the resume worker should run or not.

Then a bunch of code was just mid-layering because of incorrect assignment who
should do what.

And finally comments explaining what happens instead of why.

Just re-write it from scratch, that should at least fix some of the hangs we
are seeing.

Use RCU for the eviction fence pointer in the manager, the spinlock usage was
mostly incorrect as well. Then finally remove all the nonsense checks and
actually add them in the correct locations.

v2: some typo fixes and cleanups suggested by Sunil

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/radeon: apply state adjust rules to some additional HAINAN vairants
Alex Deucher [Mon, 25 Sep 2023 14:44:06 +0000 (10:44 -0400)] 
drm/radeon: apply state adjust rules to some additional HAINAN vairants

They need a similar workaround.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1839
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: apply state adjust rules to some additional HAINAN vairants
Alex Deucher [Mon, 25 Sep 2023 14:44:07 +0000 (10:44 -0400)] 
drm/amdgpu: apply state adjust rules to some additional HAINAN vairants

They need a similar workaround.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1839
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: rework how we handle TLB fences
Alex Deucher [Mon, 16 Mar 2026 15:04:46 +0000 (11:04 -0400)] 
drm/amdgpu: rework how we handle TLB fences

Add a new VM flag to indicate whether or not we need
a TLB fence.  Userqs (KFD or KGD) require a TLB fence.
A TLB fence is not strictly required for kernel queues,
but it shouldn't hurt.  That said, enabling this
unconditionally should be fine, but it seems to tickle
some issues in KIQ/MES.  Only enable them for KFD,
or when KGD userq queues are enabled (currently via module
parameter).

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4798
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4749
Fixes: f3854e04b708 ("drm/amdgpu: attach tlb fence to the PTs update")
Cc: Christian König <christian.koenig@amd.com>
Cc: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add JPEG_v5_0_2 IP block
Sonny Jiang [Wed, 21 Jan 2026 22:56:36 +0000 (17:56 -0500)] 
drm/amdgpu: Add JPEG_v5_0_2 IP block

Add support for JPEG_5_0_2

v2: comment out RAS for now (Alex)
v3: drop some bringup leftovers (Alex)

Signed-off-by: Sonny Jiang <sonjiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Set VCN_5_0_2 DPG mode
Sonny Jiang [Fri, 23 Jan 2026 16:08:35 +0000 (11:08 -0500)] 
drm/amdgpu: Set VCN_5_0_2 DPG mode

Set DPG flag for VCN_5_0_2

Signed-off-by: Sonny Jiang <sonjiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add VCN_5_0_2 codecs capabilities support
Sonny Jiang [Thu, 22 Jan 2026 18:23:48 +0000 (13:23 -0500)] 
drm/amdgpu: Add VCN_5_0_2 codecs capabilities support

Support VCN_5_0_2 codec query

Signed-off-by: Sonny Jiang <sonjiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add VCN v5_0_2
Sonny Jiang [Wed, 21 Jan 2026 15:02:11 +0000 (10:02 -0500)] 
drm/amdgpu: Add VCN v5_0_2

Add support for VCN_5_0_2

v2: squash in RRMT enable bit fix from Sonny (Alex)
v3: sqaush in doorbell enablement patch (Alex)
v4: drop some bringup leftovers (Alex)

Signed-off-by: Sonny Jiang <sonjiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/pm: Add mutex lock for metrics table
Asad Kamal [Sat, 31 Jan 2026 10:05:31 +0000 (18:05 +0800)] 
drm/amd/pm: Add mutex lock for metrics table

Add metrics table mutex lock in smu table context struct

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/pm: Update pm attributes
Asad Kamal [Sun, 30 Nov 2025 11:45:28 +0000 (19:45 +0800)] 
drm/amd/pm: Update pm attributes

Update pm attributes show/hide for gc_v12_1_0

v2: Use multi-aid check (Lijo)

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/pm: Add fru eeprom info support
Asad Kamal [Wed, 28 Jan 2026 08:30:01 +0000 (16:30 +0800)] 
drm/amd/pm: Add fru eeprom info support

Add fru eeprom info support for smu_v15_0_8

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/ras: Fix NULL deref in ras_core_get_utc_second_timestamp()
Srinivasan Shanmugam [Sun, 15 Mar 2026 05:59:41 +0000 (11:29 +0530)] 
drm/amd/ras: Fix NULL deref in ras_core_get_utc_second_timestamp()

ras_core_get_utc_second_timestamp() retrieves the current UTC timestamp
(in seconds since the Unix epoch) through a platform-specific RAS system
callback and is used for timestamping RAS error events.

The function checks ras_core in the conditional statement before calling
the sys_fn callback. However, when the condition fails, the function
prints an error message using ras_core->dev.

If ras_core is NULL, this can lead to a potential NULL pointer
dereference when accessing ras_core->dev.

Add an early NULL check for ras_core at the beginning of the function
and return 0 when the pointer is not valid. This prevents the
dereference and makes the control flow clearer.

Fixes: 13c91b5b4378 ("drm/amd/ras: Add rascore unified interface function")
Cc: YiPeng Chai <YiPeng.Chai@amd.com>
Cc: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Tao Zhou <tao.zhou1@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: YiPeng Chai <YiPeng.Chai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/atomfirmware: Add LpDDR5x and new fields for info v2_3
Leo Li [Fri, 13 Mar 2026 18:22:41 +0000 (14:22 -0400)] 
drm/amdgpu/atomfirmware: Add LpDDR5x and new fields for info v2_3

[Why]

Newer DCN bandwidth calculations require new definitions.

[How]

Add new fields cpu_id and vram_bit_width for
atom_integrated_system_info_v2_3, and add a memtype for LpDDR5x.

Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Fix ISP segfault issue in kernel v7.0
Pratap Nirujogi [Wed, 11 Mar 2026 16:15:09 +0000 (12:15 -0400)] 
drm/amdgpu: Fix ISP segfault issue in kernel v7.0

Add NULL pointer checks for dev->type before accessing
dev->type->name in ISP genpd add/remove functions to
prevent kernel crashes.

This regression was introduced in v7.0 as the wakeup sources
are registered using physical device instead of ACPI device.
This led to adding wakeup source device as the first child of
AMDGPU device without initializing dev-type variable, and
resulted in segfault when accessed it in the amdgpu isp driver.

Fixes: 057edc58aa59 ("ACPI: PM: Register wakeup sources under physical devices")
Suggested-by: Bin Du <Bin.Du@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/gmc9.0: add bounds checking for cid
Alex Deucher [Mon, 16 Mar 2026 19:51:08 +0000 (15:51 -0400)] 
drm/amdgpu/gmc9.0: add bounds checking for cid

The value should never exceed the array size as those
are the only values the hardware is expected to return,
but add checks anyway.

Cc: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/mmhub4.2.0: add bounds checking for cid
Alex Deucher [Wed, 4 Mar 2026 22:26:17 +0000 (17:26 -0500)] 
drm/amdgpu/mmhub4.2.0: add bounds checking for cid

The value should never exceed the array size as those
are the only values the hardware is expected to return,
but add checks anyway.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/mmhub4.1.0: add bounds checking for cid
Alex Deucher [Wed, 4 Mar 2026 22:25:56 +0000 (17:25 -0500)] 
drm/amdgpu/mmhub4.1.0: add bounds checking for cid

The value should never exceed the array size as those
are the only values the hardware is expected to return,
but add checks anyway.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/mmhub3.0: add bounds checking for cid
Alex Deucher [Wed, 4 Mar 2026 22:25:30 +0000 (17:25 -0500)] 
drm/amdgpu/mmhub3.0: add bounds checking for cid

The value should never exceed the array size as those
are the only values the hardware is expected to return,
but add checks anyway.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/mmhub3.0.2: add bounds checking for cid
Alex Deucher [Wed, 4 Mar 2026 22:25:09 +0000 (17:25 -0500)] 
drm/amdgpu/mmhub3.0.2: add bounds checking for cid

The value should never exceed the array size as those
are the only values the hardware is expected to return,
but add checks anyway.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/mmhub3.0.1: add bounds checking for cid
Alex Deucher [Wed, 4 Mar 2026 22:24:35 +0000 (17:24 -0500)] 
drm/amdgpu/mmhub3.0.1: add bounds checking for cid

The value should never exceed the array size as those
are the only values the hardware is expected to return,
but add checks anyway.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/mmhub2.3: add bounds checking for cid
Alex Deucher [Wed, 4 Mar 2026 22:24:10 +0000 (17:24 -0500)] 
drm/amdgpu/mmhub2.3: add bounds checking for cid

The value should never exceed the array size as those
are the only values the hardware is expected to return,
but add checks anyway.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/mmhub2.0: add bounds checking for cid
Alex Deucher [Wed, 4 Mar 2026 22:22:43 +0000 (17:22 -0500)] 
drm/amdgpu/mmhub2.0: add bounds checking for cid

The value should never exceed the array size as those
are the only values the hardware is expected to return,
but add checks anyway.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add default case in DVI mode validation
Srinivasan Shanmugam [Thu, 12 Mar 2026 13:59:54 +0000 (19:29 +0530)] 
drm/amdgpu: Add default case in DVI mode validation

amdgpu_connector_dvi_mode_valid() assigns max_digital_pixel_clock_khz
based on connector_object_id using a switch statement that lacks a
default case.

In practice this code path should never be hit because the existing
cases already cover all digital connector types that this function is
used for. This is also legacy display code which is not used for new
hardware.

Add a default case returning MODE_BAD to make the switch exhaustive and
silence the static analyzer smatch error. The new branch is effectively
defensive and should never be reached during normal operation.

Fixes: 585b2f685c56 ("drm/amdgpu: Respect max pixel clock for HDMI and DVI-D (v2)")
Cc: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/ras: Fix NULL deref in ras_core_ras_interrupt_detected()
Srinivasan Shanmugam [Wed, 22 Oct 2025 12:46:51 +0000 (18:16 +0530)] 
drm/amd/ras: Fix NULL deref in ras_core_ras_interrupt_detected()

Fixes a NULL pointer dereference when ras_core is NULL and ras_core->dev
is accessed in the error path.

Fixes: 13c91b5b4378 ("drm/amd/ras: Add rascore unified interface function")
Reported by: Dan Carpenter <dan.carpenter@linaro.org>
Cc: YiPeng Chai <YiPeng.Chai@amd.com>
Cc: Tao Zhou <tao.zhou1@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Drop unreachable return in amdgpu_reg_get_smn_base64()
Srinivasan Shanmugam [Thu, 12 Mar 2026 08:37:36 +0000 (14:07 +0530)] 
drm/amdgpu: Drop unreachable return in amdgpu_reg_get_smn_base64()

amdgpu_reg_get_smn_base64() returns from all control-flow paths inside
the !adev->reg.smn.get_smn_base fallback path.

For version == 1, the function returns the base address from
amdgpu_reg_smn_v1_0_get_base(). For all other versions, the default
switch branch emits a dev_err_once() and returns 0.

The trailing return 0 after the switch is therefore unreachable and is
reported by Smatch as dead code:

  drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c:317
  amdgpu_reg_get_smn_base64() warn: ignoring unreachable code

Remove the redundant return statement.

Fixes: 467ebfe65f6e ("drm/amdgpu: Add smn callbacks to register block")
Cc: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Lijo Lazar <lijo.lazar@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: validate fence_count in wait_fences ioctl
Jesse.Zhang [Fri, 13 Mar 2026 05:12:33 +0000 (13:12 +0800)] 
drm/amdgpu: validate fence_count in wait_fences ioctl

Add an early parameter check in amdgpu_cs_wait_fences_ioctl() to reject
a zero fence_count with -EINVAL.

dma_fence_wait_any_timeout() requires count > 0. When userspace passes
fence_count == 0, the call propagates down to dma_fence core which does
not expect a zero-length array and triggers a WARN_ON.

Return -EINVAL immediately so the caller gets a clear error instead of
hitting an unexpected warning in the DMA fence subsystem.

No functional change for well-formed userspace callers.

v2:
- Reworked commit message to clarify the parameter validation rationale
- Removed verbose crash log from commit description
- Simplified inline code comment

Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: move devcoredump generation to a worker
Pierre-Eric Pelloux-Prayer [Fri, 21 Feb 2025 13:45:19 +0000 (14:45 +0100)] 
drm/amdgpu: move devcoredump generation to a worker

Update the way drm_coredump_printer is used based on its documentation
and Xe's code: the main idea is to generate the final version in one go
and then use memcpy to return the chunks requested by the caller of
amdgpu_devcoredump_read.

The generation is moved to a separate worker thread.

This cuts the time to copy the dump from 40s to ~0s on my machine.

---
v3:
- removed adev->coredump_in_progress and instead use work as
  the synchronisation mechanism
- use kvfree instead of kfree
---

Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/amdgpu: Fix build errors due to declarations after labels
Jesse.Zhang [Mon, 16 Mar 2026 01:40:47 +0000 (09:40 +0800)] 
drm/amd/amdgpu: Fix build errors due to declarations after labels

In C90 (which the kernel uses with -std=gnu89), declarations must
appear at the beginning of a block and cannot follow a label. The
switch cases in amdgpu_discovery.c and gmc_v12_1.c contained variable
declarations immediately after case labels, causing the compiler to
error:

drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c:533:3: error: a label can only be
part of a statement and a declaration is not a statement

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/userq: unlock cancel_delayed_work_sync for hang_detect_work
Sunil Khatri [Thu, 12 Mar 2026 08:25:32 +0000 (13:55 +0530)] 
drm/amdgpu/userq: unlock cancel_delayed_work_sync for hang_detect_work

cancel_delayed_work_sync for work hand_detect_work should not be
locked since the amdgpu_userq_hang_detect_work also need the same
mutex and when they run together it could be a deadlock.

we do not need to hold the mutex for
cancel_delayed_work_sync(&queue->hang_detect_work). With this in place
if cancel and worker thread run at same time they will not deadlock.

Due to any failures if there is a hand detect and reset that there a
deadlock scenarios between cancel and running the main thread.

[ 243.118276] task:kworker/9:0 state:D stack:0 pid:73 tgid:73 ppid:2 task_flags:0x4208060 flags:0x00080000
[ 243.118283] Workqueue: events amdgpu_userq_hang_detect_work [amdgpu]
[ 243.118636] Call Trace:
[ 243.118639] <TASK>
[ 243.118644] __schedule+0x581/0x1810
[ 243.118649] ? srso_return_thunk+0x5/0x5f
[ 243.118656] ? srso_return_thunk+0x5/0x5f
[ 243.118659] ? wake_up_process+0x15/0x20
[ 243.118665] schedule+0x64/0xe0
[ 243.118668] schedule_preempt_disabled+0x15/0x30
[ 243.118671] __mutex_lock+0x346/0x950
[ 243.118677] __mutex_lock_slowpath+0x13/0x20
[ 243.118681] mutex_lock+0x2c/0x40
[ 243.118684] amdgpu_userq_hang_detect_work+0x63/0x90 [amdgpu]
[ 243.118888] process_scheduled_works+0x1f0/0x450
[ 243.118894] worker_thread+0x27f/0x370
[ 243.118899] kthread+0x1ed/0x210
[ 243.118903] ? __pfx_worker_thread+0x10/0x10
[ 243.118906] ? srso_return_thunk+0x5/0x5f
[ 243.118909] ? __pfx_kthread+0x10/0x10
[ 243.118913] ret_from_fork+0x10f/0x1b0
[ 243.118916] ? __pfx_kthread+0x10/0x10
[ 243.118920] ret_from_fork_asm+0x1a/0x30

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/userq: fix dma_fence refcount underflow in userq path
Sunil Khatri [Fri, 13 Mar 2026 07:11:22 +0000 (12:41 +0530)] 
drm/amdgpu/userq: fix dma_fence refcount underflow in userq path

An extra dma_fence_put() can drop the last reference to a fence while it is
still attached to a dma_resv object. This frees the fence prematurely via
dma_fence_release() while other users still hold the pointer.

Later accesses through dma_resv iteration may then operate on the freed
fence object, leading to refcount underflow warnings and potential hangs
when walking reservation fences.

Fix this by correcting the fence lifetime so the dma_resv object retains a
valid reference until it is done with the fence.i

[   31.133803] refcount_t: underflow; use-after-free.
[   31.133805] WARNING: lib/refcount.c:28 at refcount_warn_saturate+0x58/0x90, CPU#18: kworker/u96:1/188

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: fallback to default discovery offset/size in sriov guest
Hawking Zhang [Fri, 13 Mar 2026 13:32:03 +0000 (21:32 +0800)] 
drm/amdgpu: fallback to default discovery offset/size in sriov guest

In SRIOV guest environment, if dynamic critical region
is not enabled, fallback to default discovery offset
and size to ensure proper initialization

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/userq: Use kvfree instead of kfree in amdgpu_userq_signal_ioctl
Sunil Khatri [Fri, 13 Mar 2026 07:06:46 +0000 (12:36 +0530)] 
drm/amdgpu/userq: Use kvfree instead of kfree in amdgpu_userq_signal_ioctl

In function amdgpu_userq_signal_ioctl, drm_gem_objects_lookup allocates
memory via kvmalloc and hence when that memory is freed the memory
via kvfree.

Fixes: 4ca06f6fb45d ("drm/amdgpu/userq: Use drm_gem_objects_lookup in amdgpu_userq_signal_ioctl")
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: update flip bit setting of RAS bad page
Tao Zhou [Wed, 11 Mar 2026 10:52:59 +0000 (18:52 +0800)] 
drm/amdgpu: update flip bit setting of RAS bad page

The flip bit setting is different if umc number is half of original
configuration.

v2: block the flip bit setting for unsupported umc configuration.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Replace deprecated strcpy() in amdgpu_virt_write_vf2pf_data
Yicong Hui [Fri, 9 Jan 2026 16:25:14 +0000 (16:25 +0000)] 
drm/amdgpu: Replace deprecated strcpy() in amdgpu_virt_write_vf2pf_data

strcpy() is deprecated as it does not do any bounds checking (as
specified in Documentation/process/deprecated.rst).

There is a risk of buffer overflow in the case that the value for
THIS_MODULE->version exceeds the 64 characters. This is unlikely, but
replacing the deprecated function will pre-emptively remove this risk
entirely.

Replace both instances of strcpy() with the safer strscpy() function.

Changes have been compile tested.

Reviewed-by: Kees Cook <kees@kernel.org>
Signed-off-by: Yicong Hui <yiconghui@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd: fix dcn 2.01 check
Andy Nguyen [Sun, 15 Mar 2026 16:51:47 +0000 (17:51 +0100)] 
drm/amd: fix dcn 2.01 check

The ASICREV_IS_BEIGE_GOBY_P check always took precedence, because it includes all chip revisions upto NV_UNKNOWN.

Fixes: 54b822b3eac3 ("drm/amd/display: Use dce_version instead of chip_id")
Signed-off-by: Andy Nguyen <theofficialflow1996@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Fix DisplayID not-found handling in parse_edid_displayid_vrr()
Srinivasan Shanmugam [Sun, 15 Mar 2026 13:00:26 +0000 (18:30 +0530)] 
drm/amd/display: Fix DisplayID not-found handling in parse_edid_displayid_vrr()

parse_edid_displayid_vrr() searches the EDID extension blocks for a
DisplayID extension before parsing the dynamic video timing range.

The code previously checked whether edid_ext was NULL after the search
loop. However, edid_ext is assigned during each iteration of the loop,
so it will never be NULL once the loop has executed. If no DisplayID
extension is found, edid_ext ends up pointing to the last extension
block, and the NULL check does not correctly detect the failure case.

Instead, check whether the loop completed without finding a matching
DisplayID block by testing "i == edid->extensions". This ensures the
function exits early when no DisplayID extension is present and avoids
parsing an unrelated EDID extension block.

Also simplify the EDID validation check using "!edid ||
!edid->extensions".

Fixes the below:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:13079 parse_edid_displayid_vrr() warn: variable dereferenced before check 'edid_ext' (see line 13075)

Fixes: a638b837d0e6 ("drm/amd/display: Fix refresh rate range for some panel")
Cc: Roman Li <roman.li@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Jerry Zuo <jerry.zuo@amd.com>
Cc: Sun peng Li <sunpeng.li@amd.com>
Cc: Tom Chung <chiahsuan.chung@amd.com>
Cc: Dan Carpenter <dan.carpenter@linaro.org>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: remove duplicate format modifier
Erik Kurzinger [Tue, 10 Feb 2026 20:08:15 +0000 (15:08 -0500)] 
drm/amd/display: remove duplicate format modifier

amdgpu_dm_plane_get_plane_modifiers always adds DRM_FORMAT_MOD_LINEAR to
the list of modifiers. However, with gfx12,
amdgpu_dm_plane_add_gfx12_modifiers also adds that modifier to the list.
So we end up with two copies. Most apps just ignore this but some
(Weston) don't like it.

As a fix, we change amdgpu_dm_plane_add_gfx12_modifiers to not add
DRM_FORMAT_MOD_LINEAR to the list, matching the behavior of analogous
functions for other chips.

Signed-off-by: Erik Kurzinger <ekurzinger@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: switch XGMI sysfs show helpers to sysfs_emit_at()
David Baum [Fri, 13 Mar 2026 01:52:26 +0000 (20:52 -0500)] 
drm/amdgpu: switch XGMI sysfs show helpers to sysfs_emit_at()

The XGMI sysfs show helpers amdgpu_xgmi_show_num_hops() and
amdgpu_xgmi_show_num_links() currently populate the output buffer with
sprintf() and then call sysfs_emit(buf, "%s\n", buf) to append the final
newline.

Convert both helpers to use sysfs_emit_at() while tracking the current
offset. This keeps buffer construction in the sysfs helpers, avoids
feeding the output buffer back into the final formatted write, and
matches the style already used by
amdgpu_xgmi_show_connected_port_num().

Signed-off-by: David Baum <davidbaum461@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/discovery: Add braces to case statements in amdgpu_discovery_table_check()
Nathan Chancellor [Thu, 12 Mar 2026 21:46:48 +0000 (14:46 -0700)] 
drm/amdgpu/discovery: Add braces to case statements in amdgpu_discovery_table_check()

When building with a version of clang that supports the narrower
'-fms-anonymous-structs' (as opposed to the wider '-fms-extensions')
along with the associated kernel support (such as in next-20260312 [1]),
there are warnings (or errors with CONFIG_WERROR=y / W=e) from the
switch statement added by commit 47ab777c16c7 ("drm/amdgpu/discovery:
use common function to check discovery table").

  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:560:3: error: label followed by a declaration is a C23 extension [-Werror,-Wc23-extensions]
    560 |                 struct ip_discovery_header *ihdr =
        |                 ^
  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:568:3: error: label followed by a declaration is a C23 extension [-Werror,-Wc23-extensions]
    568 |                 struct gpu_info_header *ghdr =
        |                 ^
  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:576:3: error: label followed by a declaration is a C23 extension [-Werror,-Wc23-extensions]
    576 |                 struct harvest_info_header *hhdr =
        |                 ^
  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:584:3: error: label followed by a declaration is a C23 extension [-Werror,-Wc23-extensions]
    584 |                 struct vcn_info_header *vhdr =
        |                 ^
  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:592:3: error: label followed by a declaration is a C23 extension [-Werror,-Wc23-extensions]
    592 |                 struct mall_info_header *mhdr =
        |                 ^

If '-fms-extensions' were not present, this would be a hard error in
older clang versions.

Add braces to the case statements that declare variables to clear up the
warnings.

Fixes: 47ab777c16c7 ("drm/amdgpu/discovery: use common function to check discovery table")
Link: https://git.kernel.org/next/linux-next/c/0d3fccf68d9873a3c824fb70be0dbb2c4642aa90
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/ras: Pass ras poison consumption message to sriov host
YiPeng Chai [Mon, 8 Dec 2025 08:29:51 +0000 (16:29 +0800)] 
drm/amd/ras: Pass ras poison consumption message to sriov host

Pass ras poison consumption message to sriov host.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/userq: Use kvfree instead of kfree in amdgpu_userq_wait_ioctl
Sunil Khatri [Fri, 13 Mar 2026 07:03:43 +0000 (12:33 +0530)] 
drm/amdgpu/userq: Use kvfree instead of kfree in amdgpu_userq_wait_ioctl

In function amdgpu_userq_wait_ioctl, drm_gem_objects_lookup allocates
memory via kvmalloc and hence when that memory is freed the memory
via kvfree.

Fixes: 2de9353e193f ("drm/amdgpu/userq: Use drm_gem_objects_lookup in amdgpu_userq_wait_ioctl")
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/pm: Use common smu fw check function for smu15
Asad Kamal [Thu, 12 Mar 2026 07:40:13 +0000 (15:40 +0800)] 
drm/amd/pm: Use common smu fw check function for smu15

Use common smu fw check function for smu15 and remove dedicated ones

v2: Remove dedicated functions and directly use common one

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/pm: Use common smu fw check function for smu13
Asad Kamal [Thu, 12 Mar 2026 07:33:07 +0000 (15:33 +0800)] 
drm/amd/pm: Use common smu fw check function for smu13

Use common smu fw check function for smu13 and remove deicated ones

v2: Remove dedicated functions and directly use common one

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Promote DC to 3.2.374
Taimur Hassan [Fri, 6 Mar 2026 22:43:58 +0000 (17:43 -0500)] 
drm/amd/display: Promote DC to 3.2.374

This version brings along the following updates:

- Clamp dc_cursor_position x_hotspot to prevent integer overflow
- Query DC for gfx handling when setting linear tiling
- Add a buffer for boot time crc
- Silence static analysis warnings
- Plumb MRQ programming out of DML for dml2_1
- Add dcn_mrq_present Field
- Fix number of opp
- Add debugfs to disallow eDP Replay entry

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Clamp dc_cursor_position x_hotspot to prevent integer overflow
Benjamin Nwankwo [Fri, 6 Mar 2026 17:49:44 +0000 (12:49 -0500)] 
drm/amd/display: Clamp dc_cursor_position x_hotspot to prevent integer overflow

why:
Workaround for duplicate cursor. Cursor offsetting via x_hotspot attempts
to write a 32 bit unsigned integer to the 8 bit field CURSOR_HOT_SPOT_X.
This wraps cursor position back into focus if x_hotspot exceeds 8 bits,
making duplicate cursors visible

how:
Clamp x_hotspot before writing to hardware

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Signed-off-by: Benjamin Nwankwo <Benjamin.Nwankwo@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Query DC for gfx handling when setting linear tiling
Nicholas Carbones [Wed, 11 Mar 2026 06:36:05 +0000 (14:36 +0800)] 
drm/amd/display: Query DC for gfx handling when setting linear tiling

[Why]
Post-driver cases always use linear tiling yet gfx handling for this
case is improper, allowing for incorrect gfx structs to be populated and
used.

[How]
Query DC for the apporpriate linear tiling mode and populate the DCN
specific gfx version structs.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Carbones <Nicholas.Carbones@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Add a buffer for boot time crc
Tom Chung [Wed, 4 Mar 2026 09:48:00 +0000 (17:48 +0800)] 
drm/amd/display: Add a buffer for boot time crc

[Why]
We need to reserve a memory buffer for boot time crc test
during resume.

[How]
Create a buffer during boot up and send the buffer info to
DMUB.

Reviewed-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Silence static analysis warning
Gaghik Khachatrian [Thu, 26 Feb 2026 20:17:20 +0000 (15:17 -0500)] 
drm/amd/display: Silence static analysis warning

Silence static analysis warnings by ensuring swath size temporaries are
initialized before use. No functional change intended.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Plumb MRQ programming out of DML for dml2_1
Nicholas Kazlauskas [Tue, 3 Mar 2026 14:48:37 +0000 (09:48 -0500)] 
drm/amd/display: Plumb MRQ programming out of DML for dml2_1

[Why]
If the MRQ is present then these fields are also required to be
plumbed out to the requestor for programming.

[How]
Pipe the fields out through rq_dlg_get_rq_reg.

The implementation follows the previous generation in dml2_0 for DCN35
but adjusted for the new helpers and coding style of dml2_1.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Add dcn_mrq_present Field
Austin Zheng [Thu, 29 Jan 2026 22:31:19 +0000 (17:31 -0500)] 
drm/amd/display: Add dcn_mrq_present Field

[Why/How]
Add MRQ flag so it can be passed from ip_caps to ip_params

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Fix number of opp
Austin Zheng [Fri, 23 Jan 2026 20:33:13 +0000 (15:33 -0500)] 
drm/amd/display: Fix number of opp

[Why/How]
Patch number of opp based on IP caps

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Add debugfs to disallow eDP Replay entry
Ray Wu [Mon, 2 Mar 2026 02:26:51 +0000 (10:26 +0800)] 
drm/amd/display: Add debugfs to disallow eDP Replay entry

[Why & How]
Test applications need to read CRC from eDP sink side, but sink
replay feature prevents proper CRC reading and causing timeout.

Add disallow_edp_enter_replay debugfs interface to allow test apps
to temporarily disable Replay for CRC operations.

Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Wrap dcn32_override_min_req_memclk() in DC_FP_{START, END}
Xi Ruoyao [Fri, 6 Mar 2026 06:28:03 +0000 (14:28 +0800)] 
drm/amd/display: Wrap dcn32_override_min_req_memclk() in DC_FP_{START, END}

[Why]
The dcn32_override_min_req_memclk function is in dcn32_fpu.c, which is
compiled with CC_FLAGS_FPU into FP instructions.  So when we call it we
must use DC_FP_{START,END} to save and restore the FP context, and
prepare the FP unit on architectures like LoongArch where the FP unit
isn't always on.

Reported-by: LiarOnce <liaronce@hotmail.com>
Fixes: ee7be8f3de1c ("drm/amd/display: Limit DCN32 8 channel or less parts to DPM1 for FPO")
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/display: Fix uninitialized variable use which breaks full LTO
Calvin Owens [Thu, 12 Mar 2026 17:13:34 +0000 (10:13 -0700)] 
drm/amd/display: Fix uninitialized variable use which breaks full LTO

Commit e1b385726f7f ("drm/amd/display: Add additional checks for PSP
footer size") introduced a use of an uninitialized stack variable
in dm_dmub_sw_init() (region_params.bss_data_size).

Interestingly, this seems to cause no issue on normal kernels. But when
full LTO is enabled, it causes the compiler to "optimize" out huge
swaths of amdgpu initialization code, and the driver is unusable:

    amdgpu 0000:03:00.0: [drm] Loading DMUB firmware via PSP: version=0x07002F00
    amdgpu 0000:03:00.0: sw_init of IP block <dm> failed 5
    amdgpu 0000:03:00.0: amdgpu_device_ip_init failed
    amdgpu 0000:03:00.0: Fatal error during GPU init

It surprises me that neither gcc nor clang emit a warning about this: I
only found it by bisecting the LTO breakage.

Fix by using the bss_data_size field from fw_meta_info_params, as was
presumably intended.

Fixes: e1b385726f7f ("drm/amd/display: Add additional checks for PSP footer size")
Signed-off-by: Calvin Owens <calvin@wbinvd.org>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/pm: Add common smu fw check function
Asad Kamal [Thu, 12 Mar 2026 07:26:16 +0000 (15:26 +0800)] 
drm/amd/pm: Add common smu fw check function

Add common smu firmware version check function

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: fix amdgpu_userq_evict
Christian König [Thu, 22 Jan 2026 14:27:25 +0000 (15:27 +0100)] 
drm/amdgpu: fix amdgpu_userq_evict

Canceling the resume worker synchonized can deadlock because it can in
turn wait for the eviction worker through the userq_mutex.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Limit BO list entry count to prevent resource exhaustion
Jesse.Zhang [Thu, 12 Mar 2026 10:06:17 +0000 (18:06 +0800)] 
drm/amdgpu: Limit BO list entry count to prevent resource exhaustion

Userspace can pass an arbitrary number of BO list entries via the
bo_number field. Although the previous multiplication overflow check
prevents out-of-bounds allocation, a large number of entries could still
cause excessive memory allocation (up to potentially gigabytes) and
unnecessarily long list processing times.

Introduce a hard limit of 128k entries per BO list, which is more than
sufficient for any realistic use case (e.g., a single list containing all
buffers in a large scene). This prevents memory exhaustion attacks and
ensures predictable performance.

Return -EINVAL if the requested entry count exceeds the limit

Reviewed-by: Christian König <christian.koenig@amd.com>
Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add poison consumption handling for gfx v12_1
YiPeng Chai [Mon, 8 Dec 2025 08:50:53 +0000 (16:50 +0800)] 
drm/amdgpu: Add poison consumption handling for gfx v12_1

Add poison consumption handling for gfx v12_1.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Add umc ecc error handling for gmc v12_1
YiPeng Chai [Mon, 8 Dec 2025 08:23:10 +0000 (16:23 +0800)] 
drm/amdgpu: Add umc ecc error handling for gmc v12_1

Add umc ecc error handling for gmc v12_1.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amd/ras: Add unified interface to handle ras interrupts
YiPeng Chai [Mon, 8 Dec 2025 08:28:49 +0000 (16:28 +0800)] 
drm/amd/ras: Add unified interface to handle ras interrupts

Add unified interface to handle ras interrupts, some redundant
interrupt function interfaces will be removed later.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Place firmware bo in vram for A + A
Hawking Zhang [Mon, 9 Feb 2026 20:35:24 +0000 (04:35 +0800)] 
drm/amdgpu: Place firmware bo in vram for A + A

On A+A platforms, PSP requires the firmware bo
to be located in VRAM

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/mmhub_v4_2_0: expand gart aperture to gart_end on A+A
Feifei Xu [Sat, 31 Jan 2026 05:07:39 +0000 (13:07 +0800)] 
drm/amdgpu/mmhub_v4_2_0: expand gart aperture to gart_end on A+A

On A+A, sysvm aperture is used to access vram and gart. Gart is placed
right after vram. Adjust gart aperture range in mmhub for A+A.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/gmc12: Init vram_size for A + A
Hawking Zhang [Wed, 28 Jan 2026 11:18:28 +0000 (19:18 +0800)] 
drm/amdgpu/gmc12: Init vram_size for A + A

Calculate vram_size using the XGMI node segment size
and node count for A+A configurations

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/gmc12: Update connected_to_cpu flag
Hawking Zhang [Tue, 27 Jan 2026 08:07:19 +0000 (16:07 +0800)] 
drm/amdgpu/gmc12: Update connected_to_cpu flag

Query the host–GPU interface in gmc early init
phase and set xgmi.connected_to_cpu accordingly

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/gmc12: Fix VRAM base offset calculation
Hawking Zhang [Tue, 20 Jan 2026 16:12:36 +0000 (00:12 +0800)] 
drm/amdgpu/gmc12: Fix VRAM base offset calculation

Include segment size when calculating vram base offset

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/gmc12: Query host-gpu interface
Hawking Zhang [Sat, 17 Jan 2026 11:18:06 +0000 (19:18 +0800)] 
drm/amdgpu/gmc12: Query host-gpu interface

Query host-gpu interconnect type for gmc v12 devices

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Retire get_xgmi_info callback for gfxhub v12_1
Hawking Zhang [Sat, 17 Jan 2026 12:34:44 +0000 (20:34 +0800)] 
drm/amdgpu: Retire get_xgmi_info callback for gfxhub v12_1

gfxhub v12_1 is not always on. querying xgmi info
from it may not work consistently

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Query xgmi info from mmhub if available
Hawking Zhang [Sat, 17 Jan 2026 12:33:06 +0000 (20:33 +0800)] 
drm/amdgpu: Query xgmi info from mmhub if available

Query xgmi info from mmhub if available

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Implement get_xgmi_info callback for mmhub_v4_2
Hawking Zhang [Sat, 17 Jan 2026 12:25:36 +0000 (20:25 +0800)] 
drm/amdgpu: Implement get_xgmi_info callback for mmhub_v4_2

Query memory region assignment and address via mmhub

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/gmc12: Update gmc aperture base for A + A
Hawking Zhang [Sat, 17 Jan 2026 11:47:09 +0000 (19:47 +0800)] 
drm/amdgpu/gmc12: Update gmc aperture base for A + A

Query mmhub MC_VM_FB_OFFSET, XGMI_LFB_CNTL|SIZE
registers to calculate gmc apeture base address
for A + A configuration

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/gmc12: Bypass FB resize on A + A platform
Hawking Zhang [Sat, 17 Jan 2026 11:25:56 +0000 (19:25 +0800)] 
drm/amdgpu/gmc12: Bypass FB resize on A + A platform

Resizing fb bar is not needed/supported on A + A
platform.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Update gfxhub system aperture settings for A + A
Hawking Zhang [Sat, 17 Jan 2026 10:36:37 +0000 (18:36 +0800)] 
drm/amdgpu: Update gfxhub system aperture settings for A + A

Bypass the programming from SRIOV guest

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Correct mmhub system aperture settings for A + A
Hawking Zhang [Sat, 17 Jan 2026 10:31:50 +0000 (18:31 +0800)] 
drm/amdgpu: Correct mmhub system aperture settings for A + A

Disable AGP and FB apeture on all available MMHUB
instances when vmid0 page table is enabled

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu/gmc12: Set up pdb0 for vmid0 page table
Hawking Zhang [Sat, 17 Jan 2026 09:18:10 +0000 (17:18 +0800)] 
drm/amdgpu/gmc12: Set up pdb0 for vmid0 page table

Alloc, Init and free pdb0 for vmid0 page table that
is used for fb translation on A + A platform

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Init table depth and block_size for A + A
Hawking Zhang [Sat, 17 Jan 2026 08:54:52 +0000 (16:54 +0800)] 
drm/amdgpu: Init table depth and block_size for A + A

Initialize page table depth and page table block
size for 2-level gart table construction on A + A
platform

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Place gart and vram in sysvm aper for A + A
Hawking Zhang [Sat, 17 Jan 2026 08:33:40 +0000 (16:33 +0800)] 
drm/amdgpu: Place gart and vram in sysvm aper for A + A

On A + A platform, sysvm aperture is used for both
vram and gart access. In sysvm aperture, vram starts
at 0, and gart starts right after vram.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Limit physical transcation mode to A + A only
Hawking Zhang [Sat, 17 Jan 2026 08:01:20 +0000 (16:01 +0800)] 
drm/amdgpu: Limit physical transcation mode to A + A only

Only enable page table walker to snoop CPU cache
on A + A platform

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Support forcing MTYPE_RW
Harish Kasiviswanathan [Sat, 14 Feb 2026 23:28:28 +0000 (18:28 -0500)] 
drm/amdgpu: Support forcing MTYPE_RW

Set default value of module parameter amdgpu_mtype_local to -1. This
allows to force MTYPE_RW on ASICs where MTYPE_RW is not default.

v2: Fix SDMA get_vm_pte_pde MTYPE

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: Update MTYPE for GFX12.1
Harish Kasiviswanathan [Thu, 29 Jan 2026 19:17:22 +0000 (14:17 -0500)] 
drm/amdgpu: Update MTYPE for GFX12.1

Update MTYPE for GFX12.1 for AID A0 and A1

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Philip.Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdkfd: Don't expect signal mailbox update
Harish Kasiviswanathan [Wed, 28 Jan 2026 15:54:10 +0000 (10:54 -0500)] 
drm/amdkfd: Don't expect signal mailbox update

GFX12.1 CP to improve performance has removed updating event_id into
signal mailbox. In future, this optimization can be extended to older
ASICs. Update driver code to handle this case.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: update cp packets for gfx v12_1
Likun Gao [Fri, 9 Jan 2026 02:34:20 +0000 (10:34 +0800)] 
drm/amdgpu: update cp packets for gfx v12_1

Clean up some unsupport CP packets for gfx v12_1.
Update CP packets for gfx v12_1 with some new definition.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2 months agodrm/amdgpu: retire some unsupport cmd pkt bit for gfx v12_1
Likun Gao [Fri, 9 Jan 2026 05:19:38 +0000 (13:19 +0800)] 
drm/amdgpu: retire some unsupport cmd pkt bit for gfx v12_1

Retire some unsupport CP command bit set for gfx v12_1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>