econet: add EN751627 subtarget and Zyxel EX3301-T0 board
The EN751627 EcoNet subtarget consists of the EN7516 DSL SoC and the
(rare) EN7527 xPON SoC.
We currently support pci / wifi, usb and flash, but the EN751221 eth
driver is not portable to this family right now.
Zyxel EX3301-T0 is a wifi router based on the EN7516, it is a DSL SoC
but lacks the DSL port.
Installation instructions:
1. Serial access is required, stop the Zyxel bootloader.
2. Use ATENv3 https://github.com/cjdelisle/ATENv3 to unlock bootloader
3. "ATLD x" on the prompt to start a TFTP server
4. Connect ethernet cable from any lan (yellow) port on modem to a
device.
5. On your device, configure network to 192.168.1.2/30
6. On your device, send TRX file to 192.168.1.1 with name x, i.e.
tftp -p -l ./econet/tclinux -r x 192.168.1.1
7. On modem, you should see a line like this:
"Total 8022324 (0x7A6934) bytes received" note the hex value
8. "ATGU" to enter econet bootloader
9. "flash 80000 80020000 <the hex number without 0x>"
For example: flash 80000 80020000 7A6934
10. "reboot 1" -- start the system
If it boots back into the factory OS, you need to switch OS, from the
ZHAL prompt:
1. "ATCB" -- load data from flash
2. "ATCF 0" -- switch to OS 0
3. "ATBT 1" -- enable flash write
4. "ATSB" -- save data
5. "ATSR 1" -- reboot system
x86/base-files + kernel/modules: improve Dell Edge620/640/680 support
This improves on openwrt/openwrt@aeb9028aabf6bf90638a822d563f54a2c4146e6d by adding support for
other Dell EMC Edge620/640/680 devices and mapping
the interfaces to match the markings on the device.
This modifies the netdevices.mk file to set the boot flag for
ixgbe driver to load it in early stage of the boot process to
allow for proper mapping of the network interface PCI paths
inside the 02_network script. This will also allow other devices
using the ixgbe driver to do proper mapping in 02_network script.
The 02_network script is then modified to support all
dell-emc-620/640/680 devices. It now maps the network
interfaces via PCI paths to match the markings on the device.
The interface marked GE6 is still used for WAN with
interfaces GE1-GE5 used for LAN.
The SFP1 and SFP2 interfaces are left to be assigned by
the user.
!!! BACKUP YOUR ROM !!!
=======================
Please always have your FULL flash image backup before flashing
anything. The vendor firmware varies a lot depending on your ISP and
location. You will have a hard time finding the right regional firmware
if you don't have a backup.
Notes
=====
* Due to the target `econet` being incomplete, WiFi, DSA switch, and
many other features are not supported yet. Do not flash the image unless
you know the consquences or `econet` is declared stable.
* This device, and apparently many other devices of this platform, use
a dual-image layout. OpenWRT (with `econet` target) only uses slot A.
Slot B is not used by OpenWRT, and is applicable for dual-booting to
vendor firmware.
* If you do not use vendor firmware anymore, you can erase and reuse
anything after `configuration_b`, which gives you ~110 MiB free space.
Again, backup your flash first.
Installation
============
Within shell
------------
Note that acquiring the shell access to the vendor firmware can be a bit
tricky depending on the firmware variation. If you can't play with the
vendor firmware, boot to OpenWrt using debricking method below.
0. (Optional) Back up your flash, and / or move the vendor firmware to
slot B
1. Build and then locate the `kernel.bin` and `rootfs.bin` image files
2. Upload `kernel.bin` and `rootfs.bin` to the device (via HTTP or USB
stick), then type:
```
mtd write -f -e KernelA kernel.bin KernelA
mtd erase RootfsA
mtd write -f -r -e AppA rootfs.bin AppA
```
From bootloader
---------------
1. Build and then locate the `kernel.bin` and `rootfs.bin` image files
2. Switch device on and press a key within 3 seconds
3. Upload `kernel.bin` via TFTP as described below
4. Once the transfer has completed successfully, bootloader will give
you the file length in "Total %d (0x%X) bytes received", then type
`flash 200000 80020000 <file length hex>`
5. Upload `rootfs.bin` then flash with
`flash 600000 80020000 <file length hex>`
6. Restart the device to boot into OpenWRT
> [!IMPORTANT]
> Do not try `httpd` in the bootloader. It writes to the wrong address
and will corrupt the flash.
Debricking
==========
1. Build and then locate the `initramfs-kernel.bin` image files
2. Switch device on and press a key within 3 seconds
3. Connect to device via ethernet, set the IP address to `192.168.1.X`,
then upload the image via TFTP
`tftp 192.168.1.1 -m binary -v -c put initramfs-kernel.bin`
The file name can be anything except `tcboot.bin` or `tclinux.bin`,
they will corrupt the flash.
4. Type `jump 80020000` to boot the kernel from memory
Dual boot
=========
Use `en75_chboot` tool to switch between vendor firmware and OpenWrt. If
you are soft-locked, you can also switch the flag in the bootloader:
1. Switch device on and press a key within 3 seconds
2. Select the kernel that you wish to use:
- `memwl 8002000030ffffff` for `KernelA` (OpenWrt)
- `memwl 8002000031ffffff` for `KernelB` (Factory)
3. Select the rootfs, which should be the same as the kernel:
- `memwl 8002000430ffffff` for `RootfsA` (OpenWrt)
- `memwl 8002000431ffffff` for `RootfsB` (Factory)
3. Commit the data to flash: `flash 1e0000 80020000 8`
4. Restart the device to boot into the selected OS
MAC addresses
=============
`//configuration_a/factory.conf` contains MAC addresses, along with
other pre-configured settings. OpenWrt uses `brmac`, `internetmac`,
`APMAC`, and `APMAC_5G`, while `tr069mac`, `voipmac`, `priprotocolmac`,
and `PONMac` are not used for now.
econet: add PCIe driver for EN751221 and enable wifi
Extend the EN7528 PCIe driver to EN751221 with a specific PHY
tuning ritual. Also enable wifi drivers on SmartFiber XP8421-B,
TpLink Archer VR1200V v2 and Zyxel PMG5617GA.
Daniel Pawlik [Wed, 1 Apr 2026 11:20:03 +0000 (13:20 +0200)]
airoha: w1700k: drop RTL8261N phy interrupt
The AN7531N SoC has currently problems communicating using `phy_mmd_...`
when irqbalance is active. But when there is a communication error in the
interrupt handler, the interrupt will be disabled. This can usually be seen
in the logs as:
This is not a problem with the rtl8261n driver because it is not
registering an interrupt handler. But with the kernel realtek PHY driver, a
interrupt handler is registered which can trigger this problem on bootup.
To avoid is, disable the interrupt and use the PHY polling mode also wit
the upcoming realtek PHY driver support for RTL8261.
Co-authored-by: Aleksander Jan Bajkowski <olek2@wp.pl> Co-authored-by: Sven Eckelmann <sven@narfation.org> Signed-off-by: Daniel Pawlik <pawlik.dan@gmail.com> Link: https://github.com/openwrt/openwrt/pull/23078 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some W1700K and XR1701G boards with Realtek RTL8261N/RTL8261BE 10G PHYs
fail to bring up the USXGMII link on cold boot. The PHY enters a bad
state during initialization and the link stays down permanently until
power cycle.
Root cause: the GPIO reset assert/deassert timing (40ms/150ms) is too
short for the RTL8261N to complete its internal firmware load. The OEM
firmware uses 200ms/200ms.
Increase both PHY reset timings to 200ms/200ms to match OEM values.
Confirmed to fix intermittent boot failures on both W1700K (Gemtek)
and XR1701G boards.
Qingfang Deng [Mon, 11 May 2026 02:50:06 +0000 (10:50 +0800)]
ntfs: update to 2026-05-03
Update to the latest version.
Changes:
- fix NULL dereference in ntfs_index_walk_down()
- fix WSL symlink target leak on reparse failure
- conditionally enable POSIX ACL
- fix error handling in ntfs_write_iomap_end_resident()
- fix VCN overflow in ntfs_mapping_pairs_decompress()
- drop nlink once for WIN32/DOS aliases
- fix invalid PTR_ERR() usage in __ntfs_bitmap_set_bits_in_run()
- Use return instead of goto in ntfs_mapping_pairs_decompress()
The RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK macro was shifting
the 4-bit mask (0xF) by only (_extint % 2) bits instead of
(_extint % 2) * 4. This caused the mask to overlap with the adjacent
nibble when configuring odd-numbered external interfaces, selecting
the wrong bits entirely.
Align the shift calculation with the existing ...MODE_OFFSET macro.
Ryan Leung [Sat, 9 May 2026 00:42:59 +0000 (10:42 +1000)]
rockchip: add support for FriendlyELEC NanoPi M5
Ethernet LAN port is set to `eth1` (silkscreen "ETH2" and case label "2") next to the 2x USB Type-A
ports and WAN is set to `eth0` (silkscreen "ETH1" and case label "1") next to the USB Type-C port.
The USER ("reset") button serves as the reset button. A short press will reboot and a long press
will reset to factory settings (deleting all data) if using squashfs image.
MASK ("maskrom") and RCRY ("recovery") buttons are enabled but are not set to any specific function
Pressing the POWER button will `poweroff` the device and it will stay off until a power cycle.
Hardware
---------------
* SoC: RockChip RK3576 64-bit ARMv8-A 8 cores big.LITTLE (4x A72 and 4x A53)
* RAM: 3/4GB LPDDR4X or 8/16GB LPDDR5
* Ethernet: 2x GbE (SoC RGMII MAC, RTL8211F PHY)
* 3x LEDs (SYS - red / 1 (WAN) - green / 2 (LAN) - green)
* 4x Buttons (MASK ("maskrom"), RCRY ("recovery"), USER ("reset" - OpenWrt reset), POWER)
* 1x 16MiB SPI NOR on board
* 1x UFS slot for optional UFS 2.0 module (currently not supported)
* 1x microSD card slot (UHS-I)
* 1x HDMI OUT
* 1x Headphone OUT 3.5mm
* 1x M.2 M-key 2280 PCIe slot (PCIe 2.1 x1 supports NVMe SSD)
* 1x M.2 E-key *SDIO* slot for optional RTL8822CS Wi-Fi 5
* the case has integrated antennae as well as 2x knockouts
* the device tree is missing the nodes relevant to Wi-Fi operations so it's not supported for now.
* 2x USB 3.2 Gen 1 Type-A Ports
* Power: 1x USB Type-C 6V-20V with both DC and USB PD supported
* Serial: 1500000 8N1 3.3V - 2.54mm 3-pin header next to HDMI
MAC addresses
---------------
WAN (`eth0` case label "1"): generated from /sys/.../mmcblk0/cid (CID of SD card)
LAN (`eth1` case label "2"): WAN + 1
Installation
---------------
Decompress the archive of the OpenWrt sysupgrade image and write it to a microSD card using `dd`
or use Balena Etcher (no need to decompress).
Boot
---------------
Insert microSD card, set boot switch to "UFS/SD" and then supply power.
Ryan Leung [Sat, 9 May 2026 00:42:50 +0000 (10:42 +1000)]
uboot-rockchip: fix boot from SD card for rk3576
Apply pending U-Boot patches so that Rockchip RK3576 devices can boot from SD card. The problem:
"The BootROM on RK3576 has an issue loading boot images from an SD-card. This issue can be worked
around by injecting an initial boot image before TPL…and return to BootROM to load next image, TPL"
Compilation of the initial boot image has been added to the U-Boot build recipe.
Ryan Leung [Sat, 9 May 2026 00:42:39 +0000 (10:42 +1000)]
rockchip: enable SARADC; add buttons hotplug and ADC kmods to default packages
Select `CONFIG_ROCKCHIP_SARADC=y` to enable Rockchip SAR ADC
Add ADC Ladder Buttons driver as a kernel module as well as `kmod-button-hotplug` to the list of
default packages for Rockchip targets that have buttons connected to ADC, not including some
devices (e.g. NanoPi R76S) that have ADC buttons which are not in the device tree.
This is needed to use buttons on Rockchip devices that are connected to ADC and not GPIO
kernel: modules: netdevices: rtl8365mb: add support for RTL8367SB
Add chip info entry for the Realtek RTL8367SB switch. This device has
chip ID 0x6367 and version 0x0010. It exposes two external interfaces:
port 6 supports MII, TMII, RMII, RGMII, SGMII and HSGMII, while port 7
supports MII, TMII, RMII and RGMII. Use the existing 8365MB-VC jam table
for initialization.
Flash instructions:
The stock firmware is OpenWrt-based (Chaos Calmer 15.05.1).
Flash the OpenWrt sysupgrade image via vendor Web UI at 192.168.99.1
(admin/admin), section System - Firmware Upgrade.
Recovery (requires UART access):
- UART: Connect to ttyS0 @ 57600, press 4 during boot delay (5 seconds)
- TFTP: Server 10.10.10.3, client 10.10.10.123, load image to 0x80000000
Matt Brent [Tue, 3 Feb 2026 23:54:58 +0000 (01:54 +0200)]
ramips: add support for Ruijie RG-EW1300G (V1.00)
The RG-EW1300G is a router with 1 x WAN and 3 x LAN gigabit ports.
The router runs on Ruijie OS by default.
- Specifications:
* SoC: MT7621A
* RAM: 128MB DDR3
* Flash: 16MB SPI NOR flash (GD25Q128C)
* WiFi0: Mediatek MT7615 2.4GHz 802.11b/g/n
* WiFi1: Mediatek MT7615 5GHz 802.11ac
* Ethernet: MT7530, 4x 1000Base-T.
* UART: Serial console - As marked on PCB, baudrate is 57600. DO NOT CONNECT 3.3V.
* Buttons: Reset, WPS.
* LED: Programmable LEDs via GPIO working for Red+Green status, and Mesh/WPS at the rear of the chassis.
- Default Flash:
```
GD25Q128C(c8 40180000) (16384 Kbytes)
mtd .name = raspi, .size = 0x01000000 (16M) .erasesize = 0x00010000 (64K) .numeraseregions = 0
6 cmdlinepart partitions found on MTD device raspi
Creating 6 MTD partitions on "raspi":
0x000000000000-0x000000050000 : "u-boot"
0x000000050000-0x000000060000 : "u-boot-env"
0x000000060000-0x000000070000 : "Factory"
0x000000070000-0x000000080000 : "product_info"
0x000000080000-0x000000090000 : "kdump"
0x000000090000-0x000001000000 : "firmware"
0x00000031a847-0x000001000000 : "rootfs"
mtd: partition "rootfs" must either start or end on erase block boundary or be smaller than an erase block -- forcing read-only
mtd: partition "rootfs_data" created automatically, ofs=0xae0000, len=0x520000
0x000000ae0000-0x000001000000 : "rootfs_data"
register mt_drv
```
1. Open the case, solder to the marked 4 pin header
2. Connect it to a USB-UART TTL (do not connect to 3.3v)
3. Open a terminal with baud 57600.
4. Power on device, and repeatedly press "2" key to catch bootloader option
5. Set IP, TFTP server IP, and image file to load (eg, openwrt-ramips-mt7621-ruijie_rg-ew1300g-v1-squashfs-sysupgrade.bin)
6. System will reboot into OpenWRT.
The nRESET pins of the RTL8224 PHYs on the PSX8/PSX10 are wired to GPIO6
(lan1-4) + GPIO10 (lan5-8) of the SoC, but this was never described in the
devicetree.
GPIO 6 is the global reset shared by (logical) PHYs 0-3 on MDIO bus0. GPIO
10 is the global reset shared by (logical) PHYs 8-11 on mdio bus0. It is
intentionally not declared as reset-gpios on any bus: the MDIO driver /
phylink only support a single reset GPIO per bus, not two (or more). And a
GPIO can only be used as reset-gpio on a single PHY. Attaching it to a
single PHY would still reset the other PHYs on the same chip as a side
effect, leaving their software state out of sync with the hardware and
likely breaking them.
The nRESET pins of the RTL8224 PHYs on the PSX28/ESX28 are wired to GPIO29
of the SoC, but this was never described in the devicetree.
GPIO 29 is the global reset shared by all PHYs across all MDIO busses. It
is intentionally not declared as reset-gpios on any bus: the MDIO driver /
phylink only support a reset GPIO per bus, not on the parent controller.
Attaching it to a single bus would still reset the PHYs on the other busses
as a side effect, leaving their software state out of sync with the
hardware and likely breaking them.
Remove the four T8 screws on the bottom of the device under the rubber feet.
Using a guitar pick or similar plastic tool, insert it on the side between
the bottom case and the side, pry up gently. The plastic bottom has 18 latches
around the perimeter (but none on the rear by the Ethernet ports).
Remember to remove the SIM tray!
Gently remove the metal RF shield on the bottom of the PCB.
The TSOP48 NAND flash (U30, Spansion S34ML01G200TFV00) is located on the bottom
side of the PCB (facing you as you remove the bottom plastic). To flash, you
will need to desolder the TSOP48. Attempts to flash in-circuit using a 360 clip
were unsuccessful.
The SOIC8 I2C EEPROM (U32, Atmel 24C64) is located on the bottom side of the PCB
under a metal RF shield. It can be flashed in circuit using a chip clip. You may
have to bend the RF shield up to fit the chip clip.
The UART header is on the top (opposite) side of the PCB. You do not need to
remove any more screws to remove the PCB. The PCB has some thermal interface
material for heat dissipation and will be slightly difficult to remove the
first time. Gently pry up on the green PCB from one of the front corners until
the thermal pads break contact with the top case. You can then lift out the
entire PCB, including the attached LTE/WiFi antennas.
Installation:
The dumps to flash can be found in this repository:
https://github.com/halmartin/meraki-openwrt-docs/tree/main/z3c
The device has the following flash layout (offsets with OOB data):
```
0x000000000000-0x000000100000 : "sbl1"
0x000000100000-0x000000200000 : "mibib"
0x000000200000-0x000000300000 : "bootconfig"
0x000000300000-0x000000400000 : "qsee"
0x000000400000-0x000000500000 : "qsee_alt"
0x000000500000-0x000000580000 : "cdt"
0x000000580000-0x000000600000 : "cdt_alt"
0x000000600000-0x000000680000 : "ddrparams"
0x000000700000-0x000000900000 : "u-boot"
0x000000900000-0x000000b00000 : "u-boot-backup"
0x000000b00000-0x000000b80000 : "ART"
0x000000c00000-0x000007c00000 : "ubi"
```
* Dump your original NAND (if using nanddump, include OOB data).
* Decompress `u-boot.bin.gz` dump (contains OOB data) and overwrite the
`u-boot` portion of NAND from `0x738000-0x948000` (length `0x210000`).
* Decompress `ubi.bin.gz` dump (contains OOB data) and overwrite the `ubi`
portion of NAND from `0xc60000-0x8400000` (length `0x77a0000`).
* Dump your original EEPROM. Change the byte at offset `0x49` to `0x1e`
(originally `0x2a`). Remember to re-write the EEPROM with the
modified data.
* This can be done on Linux via the following command:
`printf "\x1e" | dd of=/tmp/eeprom.bin bs=1 seek=$((0x49)) conv=notrunc`
**Note**: the device will not boot if you modify the board major number and
have not yet overwritten the `ubi` and `u-boot` regions of NAND.
* Resolder the NAND after overwriting the `u-boot` and `ubi` regions.
OpenWrt Installation:
* After flashing NAND and EEPROM with external programmers. Plug in an
Ethernet cable and power up the device.
* The new U-Boot build uses the space character `" "` (without quotes) to
interrupt boot.
* Interrupt U-Boot and `tftpboot` the OpenWrt initramfs image from your
tftp server
```
dhcp
setenv serverip <your_tftp>
tftpboot openwrt-ipq40xx-generic-meraki_z3c-initramfs-uImage.itb
```
* Once booted into the OpenWrt initramfs, created the `ART` ubivol with
the WiFi radio calibration from the mtd partition:
```
cat /dev/mtd10 > /tmp/ART.bin
ubiupdatevol /dev/ubi0_1 /tmp/ART.bin
```
* `scp` the `sysupgrade` image to
the device and run the normal `sysupgrade` procedure:
```
scp -O openwrt-ipq40xx-generic-meraki_z3c-squashfs-sysupgrade.bin root@192.168.1.1:/tmp/
ssh root@192.168.1.1 "sysupgrade -n /tmp/openwrt-ipq40xx-generic-meraki_z3c-squashfs-sysupgrade.bin"
```
* OpenWrt should now be installed on the device.
* Note: To use the LTE modem as a WWAN, you must install `modemmanager`
(you probably also want `luci-proto-modemmanager`) and then configure
the modem for your provider.
Due to OpenWrt policies these packages are not included in the
initramfs/sysupgrade image.
Hal Martin [Tue, 12 May 2026 10:41:59 +0000 (12:41 +0200)]
ipq40xx: remove unused dtsi for Meraki devices
Remove target/linux/ipq40xx/dts/qcom-ipq4029-wired-qca-common.dtsi
This file is no longer used after the ipq40xx Meraki device tree
refactoring that occurred last year when adding support for the MR30H.
Hauke Mehrtens [Tue, 12 May 2026 20:31:41 +0000 (22:31 +0200)]
toolchain: musl: backport patches with CVE fixes
This fixes:
* CVE-2026-6042: Algorithmic Complexity DoS in musl libc iconv
* CVE-2026-40200: musl libc: stack corruption in qsort with sufficiently large inputs
Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi> Link: https://github.com/openwrt/openwrt/pull/23330
[Added this to main branch first] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
airoha: update PCS node in DTSI for new PCS implementation
Update the PCS node in AN7581/AN7583 .dtsi for new PCS implementation.
The #pcs-cell is now needed for the produced/consumer implementation.
Also add entry for USB and PCIe PCS for AN7581 but keep them disabled
by default. USB and PCIe PCS for AN7583 node will be added later once PHY
code will stabilize.
Migrate Airoha PCS/Ethernet pending patch to PCS standalone implementation.
This new implementation drop the hack of reading and accessing the dev from
a different device and drop the legacy pcs_create/drop implementation in
favor of fwnode one with a provider/consumer approach.
This is also to sync with the proposed series posted upstream for revision.
The new PCS patch for AN7581 implement full support for USB and PCIe PCS.
Backport phylink_replay_link() API patch from upstream kernel. This is
mostly needed for force_major_config bool in phylink struct needed for new
standalone PCS series.
While at it also rename the current 703 patch to 703-01 as it's part of the
same series merged upstream.
With Kernel 6.18 the kernel size exceeds 4MB. Without additional changes
to the partition layout or kernel size reduction, the image will not be
usable. Disable this sub-target until necessary changes or a decision
regarding its removal have been made.
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
wireguard-tools: increase watchdog idle timeout to 180s
The current 150s watchdog timeout is too aggressive, leading to
premature hostname re-resolution on alive connections.
Even with a 25s keepalive, handshakes may not occur within the 150s window.
Increasing the timeout to 180s aligns the watchdog with WireGuard's
REJECT_AFTER_TIME constant, ensuring we only re-resolve when the connection
is truly considered dead.
Chukun Pan [Wed, 6 May 2026 12:30:16 +0000 (20:30 +0800)]
mediatek: fix patch to enable an8855 eFuse
Although the AN8855 eFuse driver was merged upstream, other
drivers were not. Restore Kconfig dependencies to enable it.
Also remove useless change logs from the patch.
Fixes: 2129465 ("mediatek: fix patches for Linux 6.18") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/23250 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Hauke Mehrtens [Sun, 10 May 2026 14:34:54 +0000 (16:34 +0200)]
github: separate concurrency group per event for kernel and packages
Manual workflow_dispatch and push share the same ref on main, so
they previously landed in the same concurrency group
'Build Kernel-refs/heads/main' (and the equivalent for the packages
workflow). With cancel-in-progress: false for non-PR events, only
one run can be pending per group: a newer queued run cancels the
older pending one.
That made the manual trigger unreliable in both directions. A push
landing while a dispatch was queued displaced the dispatch (so the
ccache reseed never ran), and dispatching while a push was queued
displaced the push (so the legitimate per-commit build was lost).
Adding github.event_name to the concurrency group puts pushes,
dispatches, and pull_requests in separate buckets on the same ref,
so they no longer compete with each other.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Link: https://github.com/openwrt/openwrt/pull/23283 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Hauke Mehrtens [Sun, 10 May 2026 14:27:26 +0000 (16:27 +0200)]
github: add workflow_dispatch trigger to kernel and packages
Allow the Build Kernel and Build all core packages workflows to be
launched manually from the Actions tab. The shared workflow side
detects workflow_dispatch and, for Build Kernel, rebuilds the full
target/subtarget matrix including testing kernel versions, so a
manual run can re-seed the s3 ccache when a queued push run got
displaced from the concurrency queue by the next commit on main.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Link: https://github.com/openwrt/openwrt/pull/23283 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Russell Senior [Thu, 23 Apr 2026 05:38:51 +0000 (22:38 -0700)]
airoha: increase the size of reserved_bmt partition
The vendor firmware checks for a bmt header in the last 528 erase blocks
of flash. The OpenWrt partition table did not respect that requirement,
and therefore the vendor and openwrt chainloader fight over those blocks
on every boot, potentially corrupting data stored in UBI blocks there.
This commit increases the size of the reserved_bmt partition to avoid
that fight.
Although the vendor bootloader only seems to touch the final 250 erase
blocks[1], the original vendor firmware system partition ended at
0x1be00000[2], so to be conservative, the consensus is to use that as
the end of mtd2 (ubi) partition and leave the last 528 blocks for mtd3
(reserved_bmt).
From https://openwrt.org/toh/gemtek/mxf-w1700k:
[1] OEM bootlog: [ 5.324337] bmt pool size: 250
[2] OEM bootlog: [ 5.478927] 0x000008600000-0x00001be00000 : "system"
Adds a compat_version to warn users to re-install to accomodate the
shrunken mtd2 ubi partition.
Fixed two nits suggested by Claude, zero padding a hex value and removed
an extra space.
Removed the wildcard setting of compat_version for other boards, as
suggested by Robert Marko, set compat_version only for the w1700k.
Reported-by: Loïc Yhuel <loic.yhuel@gmail.com> Signed-off-by: Russell Senior <russell@personaltelco.net> Link: https://github.com/openwrt/openwrt/pull/23061 Signed-off-by: Robert Marko <robimarko@gmail.com>
Jonas Jelonek [Sun, 10 May 2026 18:44:30 +0000 (18:44 +0000)]
realtek: pcs: rtl930x: drop superfluous debug prints
The RTL930x calibration code is especially chatty. There are debug
prints for every start and end of a section corresponding to the
sections the SDK uses. In the end, this doesn't help a user much and
just wastes CPU cycles. Moreover it doesn't help in understand what is
done there. As a first step, drop "start" and "end" prints but preserve
their meaning as comments.
While at it, slightly adjust two other prints and drop one confusing
print.
Jonas Jelonek [Sat, 9 May 2026 21:25:51 +0000 (21:25 +0000)]
realtek: pcs: rtl930x: reduce chattiness and reg ops
There is no need to be extra chatty for simple writes which set a single
bit. As a nice side effect, without the prints there's no need to have
open-coded register access when there a helper that covers that.
Jonas Jelonek [Sat, 9 May 2026 20:31:46 +0000 (20:31 +0000)]
realtek: pcs: rtl931x: reduce chattiness
The SerDes setup code for RTL931x still has a lot of debug prints as
pr_info from former times. A lot has changed and we don't need that
rather useless chattiness anymore. We reached a state where we have a
standalone setup of most hardware modes. The registers printed are still
"documented" in rtpcs_931x_sds_config_hw_mode and
rtpcs_93xx_sds_config_cmu. For every other issues we rely on comparison
of full SerDes dumps instead of cherry-picked registers.
Flashing OpenWrt will overwrite BootExtension + ZyNOS. BootExtension
functionality is not available anymore then. The U-boot/Bootbase still
has some limited functionality which can be used in emergency cases.
Installation
============
Simple web upgrade:
1. Take the OpenWrt factory.bin image generated by the build.
2. In the ZyNOS web UI, login and go to Maintenance -> Firmware Upgrade.
3. Under "Boot Image", make sure the Config Boot Image is set to 1. In
other words, make sure the switch booted from firmware image 1 or it
will do so on next reboot.
This is crucial, otherwise OpenWrt cannot boot.
4. Below, select and upload the factory.bin image. After clicking
upgrade, the image will be flashed.
5. After flashing has finished, reboot the switch. It will now boot into
OpenWrt.
U-Boot
======
This device ships with U-boot masked as Bootbase. After the device is
powered, a DRAM test is performed. Spamming $ during that test will drop
you into a shell after test finished. You'll have a limited command set
at first.
Unlocking the shell with [1] or [2] will give you a normal U-boot
command set. From here, you can perform initramfs boot or recovery.
Initramfs boot:
> loady 0x82000000 + go 0x82000000
Recovery:
> upgradeY image2 0x82000000 115200
Return to stock firmware
========================
1. Download the firmware for the switch from Zyxel website.
2. Unzip the download, there should be a .bin file with a alphanumeric
name.
3. Upload this file to running OpenWrt.
4. Run (use -F since the image doesn't have image metadata):
> sysupgrade -F <stock-firmware>.bin
5. Wait for the sysupgrade to succeed and the switch reboot. At the next
boot, ZyNOS should come up again.
Jonas Jelonek [Thu, 30 Apr 2026 21:32:29 +0000 (21:32 +0000)]
realtek: dts: rtl930x: add pinctrl and pinmux for UART1
RTL930x SoCs have a second serial interface UART1 which is exposed on
dual-function pins shared with JTAG. The SoC defaults to the JTAG
functionality after reset. Similar to existing pinmux registers, there's
a separate register for that where a selector decides about JTAG vs
UART.
Add a now pinctrl node for that register and a pinmux node to enable
UART1 functionality. Reference the pinmux in the (by default disabled)
uart1 node. Without this, UART1 doesn't work when it is actually needed.
This is e.g. the case with some PoE-capable switch where the PSE MCU
communicates with the SoC via UART instead of I2C.
Jonas Jelonek [Tue, 28 Apr 2026 20:53:52 +0000 (20:53 +0000)]
realtek: make Zyxel XMG1915-10E generic for whole family
The XMG1915 is a switch family with multiple variants sharing nearly
all hardware (same SoC, PHYs, SFP cages, LEDs) and mainly differing
in PoE and minor details.
In preparation for adding further variants, move the bulk of the
device tree into a shared rtl9302_zyxel_xmg1915.dtsi and reduce the
per-device dts to the device identity (compatible, model) plus any
variant-specific nodes.
For images, factor a Device/zyxel_xmg1915 template holding the shared
build settings so per-device definitions only need DEVICE_MODEL.
Jonas Jelonek [Tue, 28 Apr 2026 21:21:23 +0000 (21:21 +0000)]
realtek: support web vendor upgrade for XMG1915-10E
So far the XMG1915-10E used the rt-loader-bootbase recipe which
produces a separate loader.bin and only allows installation/upgrade
from the CLI side, not via the Zyxel web UI.
Switch to the standard zyxel_zynos image recipe shared with the other
Zyxel rtl930x devices. The loader now lives inside the 'factory'
parent partition introduced in the previous commit, so the resulting
single sysupgrade image can be flashed both from the vendor web UI
and via sysupgrade. Hook the device into the existing xs1930 case in
platform.sh which sets PART_NAME=factory and calls default_do_upgrade.
This makes the installation and revert procedure in 94607d6285cc
("realtek: add support for Zyxel XMG1915-10E") mostly obsolete and
partly not working anymore (due to different build images that are
emitted).
Jonas Jelonek [Tue, 28 Apr 2026 21:00:24 +0000 (21:00 +0000)]
realtek: fix Zyxel XMG1915-10E partition layout
When support for this device was added, the partition layout was defined
in a way that doesn't use space as intended and wastes quite a lot of
it.
(1) firmware partition starts at offset 0x1260000. This is the second
partition/B partition in the A/B scheme used by Zyxel. While the
commit mentions the image is written to A, the firmware partition
is defined in the B space.
(2) firmware partition only ~16MB in size. The device has a total of
32MB of flash. The vendor uses an A/B scheme but OpenWrt doesn't use
it. Thus, OpenWrt can make use of the full available space.
(3) loader partition too big. Other devices using rt-loader explicitly
in a partition use a size of 0x10000. This is more than enough
already. The device here uses 0x30000 which is mostly wasted.
Those issues are fixed accordingly. While at it, move partitions 'loader'
and 'firmware' into a parent partition 'factory'. This is a preparation
for adding web upgrade support for this device.
Fixes: 94607d6285cc ("realtek: add support for Zyxel XMG1915-10E") Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/23218 Signed-off-by: Robert Marko <robimarko@gmail.com>
Until now there is a O(n) loop that looks up a port for a
given bus/phy combination. This is slow for high port count
devices (RTL839x and RTL931x). Implement a efficient reverse
lookup table for that.
While we are here adapt tiny bits of the documentation to
better reflect the driver logic after the recent refactoring.
realtek: mdio: change prefix from "rtmdio_" to "rtmd_"
The long prefix distracts the reader from the real variables,
functions and defines. Shorten it to "rtmd_" that is not
used by any other upstream driver.
- low level functions do a bulk write
- high level functions have device specific structures
Turn this upside down and hide the register logic in the low
level functions. To achieve this:
- add a register map to each device
- change the low level write to use this map
- use only one common unique command structure
- use the command structure in the high level functions
While we are here fix the RTL838x access patterns. The read
functions do not need to set the bitmask.
Be consistent with the rest of the code and make clear when the
driver accesses ports. For this rename num_phys to num_ports.
Additionally make the device specific port numbers a define and
use them in the configuration structure.
Hauke Mehrtens [Sun, 3 May 2026 20:21:05 +0000 (22:21 +0200)]
libubox: update to Git HEAD (2026-05-03)
895f92164b66 uloop: add ULOOP_PRIORITY support for EPOLLPRI events f9b1f3ff17ba uloop: revert my flag changes from the ULOOP_PRIORITY change 2982bfb1c325 blob: fix wrong type for realloc result in blob_buffer_grow() 78c20f6c8579 json_script: convert recursive __json_script_file_free() to iterative e7c13bf8cbca usock: fix off-by-one in nanosecond normalization in poll_restart() 68b3f1588de4 uloop: usock: add error checking for fcntl and remove duplicate include 03821f942c49 uloop: fix undefined behavior in signal bit operations for signals > 32 e6e6fd83e26d blobmsg: fix policy name length overflow and add bounds check in blobmsg_parse() d30b9cc1a02d usock: fix integer overflow in timeout calculations 406e342bb900 udebug: fix double off-by-one in udebug_entry_vprintf() 700eca0bac66 blobmsg_json: fix integer overflow in blobmsg_puts() 6351fe552162 blobmsg_json: floor strbuf size and tighten the post-format guard 58b6543f1b25 blobmsg: fix unsigned integer overflow in blobmsg_alloc_string_buffer() d7a3ae699df0 blobmsg: use correct byte-order macro when setting BLOB_ATTR_EXTENDED 23c6618a5b90 blobmsg_json: fix double format string to avoid truncation and data loss 1edf1d704e76 jshn: fix integer overflow and type confusion in jshn_parse_file 9b488010c4a7 utils: fix integer overflow in __calloc_a() 40a87f734b94 blob: fix integer overflow in buffer growth functions 02fccb465651 blob: use size_t for blob_memdup() length 0fa612ca08f7 json_script: avoid alloca() on attacker-controlled pattern length 8c9862b6921b blobmsg: fix integer overflow in blobmsg_realloc_string_buffer() 5fbef5bb94fb ustream: avoid INT_MAX overflow on malloc in ustream_vprintf() 1501e60e5554 md5: detect read errors in md5sum() instead of returning a bogus hash
x86/base-files: add support for CloudGenix ION 2000
The CloudGenix ION 2000 is a discontinued entry-level SD-WAN appliance,
a rebranded Lanner FW-7525 based on the Intel Atom C2XXX family of processors
with 4 integrated GbE ports and 2 additional I210 GbE ports. It can often be
found on eBay starting below USD 30.
The device's BIOS is password-protected, and the password somehow hasn't leaked,
but OpenWrt can be successfully booted by overwriting the stock OS on the boot
media.
See https://forum.openwrt.org/t/report-openwrt-on-cloudgenix-ion-2000/249315
for more details.
The two I210 NICs and integrated NICs are pinned to their
PCIe paths to ensure consistent interface ordering matching
the physical port layout with eth0 assigned to controller and
acting as WAN with remaining devices as LAN.
Rosen Penev [Thu, 4 Dec 2025 03:15:05 +0000 (19:15 -0800)]
ath79: fix label-mac-device for wmac
It appears 683-of_net-add-mac-address-to-of-tree.patch relies on the
mac-address nvmem property being present. wmac itself doesn't need it as
it takes it from the eeprom but label-mac-device needs it.
Ahmed Naseef [Thu, 19 Mar 2026 11:55:28 +0000 (15:55 +0400)]
econet: en7528: add USB support
Add USB host support for EN7528 SoC:
- New phy-en7528-usb driver with U2 slew rate calibration and U3
RX impedance tuning, based on GPL vendor code and the Airoha
AN7581 USB PHY driver
- xHCI LTSSM timing quirk for TD 6.5 compliance (patch 915)
- USB PHY and xHCI DTS nodes with IPPC register mapping
- VBUS power via regulator-fixed for DASAN H660GM-A
- Enable USB, xHCI, PHY, and regulator kernel configs
kmod-sound-midi2 expects sound/core/snd-ump.ko, but
CONFIG_SND_UMP=y builds it in-kernel rather than as
a module. Replace the forced built-in setting with
plain CONFIG_SND_UMP so the module can be packaged
correctly.
mediatek: add support for Qihoo 360T7 (UBI layout)
This commit adds support for Qihoo 360T7 (UBI layout).
Aims
----
1. +20 MB additional free space for the packages
2. More reliable storage for the factory and fip partitions (in UBI)
Install (from non-UBI OpenWrt)
------------------------------
1. Navigate http://192.168.1.1/ and download mtd backups
2. Upgrade OpenWrt with installer initramfs image (force upgrade, don't
keep settings). Wait until OpenWrt reboots and until installer:
- Prepare new factory partition
- Format new ubi
- Make ubi volumes
- Write new fip and bl2
3. Navigate http://192.168.1.1/ and Upgrade with OpenWrt 'sysupgrade.bin'
image (don't keep settings)
Qingfang Deng [Fri, 24 Apr 2026 01:44:32 +0000 (09:44 +0800)]
kernel: enable static key
Enable static key (jump label) on all supported architectures. This
lowers overhead and stress on the branch prediction of the CPU and
generally makes the kernel faster.
mediatek,mtd-eeprom predates nvmem and is being phased out.
At first glance, it looks like it's doing something useful with its
big-endian binding. However on further inspection, big-endian is handled
in the same function that mediatek,mtd-eeprom is handled. In addition,
the older mtd_read way of extracting the firmware byteswaps the data
on big endian hosts which big-endian byteswaps back. nvmem does not do
such byteswapping.
Zoltan HERPAI [Mon, 9 Feb 2026 09:34:37 +0000 (09:34 +0000)]
sunxi: add T113-S3 support
The Allwinner T113-s3 (sun8i) SoC features a dual-core Cortex-A7 ARM CPU and
128MB of DDR3 memory in the same physical package. It supports industrial
temperature ranges. Most of the IP blocks are shared with the D1/D1s core.
There are multiple variants of the SoC, which may vary in the included memory
size, with some of them including a C906 RISC-V co-processor.
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
projects / thirdparty / openwrt.git / log
