Peter Maydell [Fri, 27 Mar 2026 11:16:08 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Add defines for GICv5 architected PPIs
The GICv5 defines architected numbers for the PPI sources like the
generic timer and the PMU; these are different from the ones
traditionally used by GICv2 and GICv3. Add defines for them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-14-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:16:07 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Implement gicv5_class_name()
Implement a gicv5_class_name() function that does the same job as
gicv3_class_name(): allows board code to get the correct QOM type for
the GIC at runtime depending on whether KVM is enabled or not.
For the GICv5, we don't yet implement KVM support, so the KVM-enabled
codepath is always an error.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-13-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:16:06 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA
The GICv5 IRS keeps data structures in system memory. (Notably, it
stores per-interrupt configuration information like the interrupt
priority and its active and pending state in an in-memory data
structure.) Add a link property so that the board or SoC can wire up
a MemoryRegion that we will do DMA to. We name this property
"sysmem" to match the GICv3's equivalent property.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-12-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:16:05 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Implement IRS ID regs
Implement the IRS frame ID registers IRS_IDR[0-7], IRS_IIDR and
IRS_AIDR. These are all 32-bit registers.
We make these fields in the GIC state struct rather than just
hardcoding them in the register read function so that we can later
code "do this only if X is implemented" as a test on the ID register
value.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-11-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:16:04 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Define macros for config frame registers
Define constants for the various registers in the IRS config frame
using the REG and FIELD macros.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-id: 20260327111700.795099-10-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:16:03 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Create inbound GPIO lines for SPIs
The GICv5 IRS may have inbound GPIO lines corresponding to SPIs
(shared peripheral interrupts). Unlike the GICv3, it does not deal
with PPIs (private peripheral interrupts, i.e. per-CPU interrupts):
in a GICv5 system those are handled entirely within the CPU
interface. The inbound GPIO array is therefore a simple sequence of
one GPIO per SPI that this IRS handles.
Create the GPIO input array in gicv5_common_init_irqs_and_mmio().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-9-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:16:02 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Create and validate QOM properties
Add code to the GICv5 skeleton which creates the QOM properties which
the board or SoC can use to configure the GIC, and the validation
code to check they are in range. Generally these correspond to
fields in the IRS ID registers, and the properties are named
correspondingly.
Notable here is that unlike the GICv3 (which assumes its connected
CPUs are the system's CPUs starting from 0), we define a QOM array
property which is an array of pointers to the CPUs, and a QOM array
property which is an array of integers telling the GIC what the
IAFFID (interrupt affinity ID) for each CPU is; so a board or SoC
which wants to connect multiple CPUs to this GICv5 would do something
like:
for (int i = 0; i < ms->smp.cpus; i++) {
qlist_append_link(cpulist, OBJECT(qemu_get_cpu(i)));
qlist_append_int(iaffidlist, i);
}
qdev_prop_set_array(vms->gic, "cpus", cpulist);
qdev_prop_set_array(vms->gic, "cpu-iaffids", iaffidlist);
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-8-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:16:01 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Add migration blocker
This initial version of the GICv5 will not support migration:
* the spec is still only at EAC level, so the data to be
migrated might in theory change before it is finalised
* when we add support for missing features like EL2/EL3/Realm
we might find we want to refactor the data structures we use
* I still need to check against the proposed KVM GICv5
handling to see if there are any awkward mismatches
that might affect how we want to store the data
* it's experimental, so for pragmatic reasons I'm skipping
it to get the initial version done faster
Install a migration blocker to enforce this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-id: 20260327111700.795099-7-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:16:00 +0000 (11:16 +0000)]
hw/intc/arm_gicv5: Implement skeleton code for IRS register frames
The GICv5 IRS has one mandatory register frame (the config frame) for
each of up to four supported physical interrupt domains. Implement
the skeleton of the code needed to create these as sysbus MMIO
regions.
The config frame has a mix of 32-bit and 64-bit registers, and it is
valid to access the 64-bit registers with 32-bit accesses. In a
similar way to the various GICv3 devices, we turn the MemoryRegionOps
read_with_attrs and write_with_attrs calls into calls on functions
specifically to read 32 or 64 bit values. (We can't trivially
implement one in terms of the other because various registers have
side effects on write which must only trigger when the "correct" half
of the 64-bit register is written to.)
Unlike the GICv3, we choose to expose a sysbus MMIO region for each
interrupt domain even if the config of the GICv5 means that it
doesn't implement that domain. This avoids having the config frame
for a domain ending up at a different MMIO region index depending on
the config of the GICv5. (This matters more for GICv5 because it
supports Realm, and so there are more possible valid configurations.)
gicv5_common_init_irqs_and_mmio() does not yet create any IRQs, but
we name it this way to parallel the equivalent GICv3 function and to
avoid having to rename it when we add the IRQ line creation in a
subsequent commit.
The arm_gicv5_types.h header is a little undermotivated at this
point, but the aim is to have somewhere to put definitions that we
want in both the GIC proper and the CPU interface.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-id: 20260327111700.795099-6-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:15:59 +0000 (11:15 +0000)]
hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board
When building the Arm "virt" board, pull in the GICv5.
We haven't added support for creating or wiring up the GICv5 in that
board yet, but adding it to the Kconfig early means that the GICv5
code will be compiled and so we can have more confidence that the
individual commits building it up are correct (or at least compile).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-5-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:15:58 +0000 (11:15 +0000)]
hw/intc: Skeleton of GICv5 IRS classes
This commit adds the skeleton of the classes for the GICv5 IRS
(Interrupt Routing Service). Since the IRS is the main (and only
non-optional) part of the GICv5 outside the CPU, we call it simply
"GICv5", in line with how we've handled the GICv3.
Since we're definitely going to need to have support for KVM VMs
where we present the guest with a GICv5, we use the same split
between an abstract "common" and a concrete specific-to-TCG child
class that we have for the various GICv3 components. This avoids
having to refactor out the base class later.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-4-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:15:57 +0000 (11:15 +0000)]
hw/core: Permit devices to define an array of link properties
Currently we allow devices to define "link properties" with
DEFINE_PROP_LINK(): these are a way to give a device a pointer to
another QOM object. (Under the hood this is done by handing it the
canonical QOM path for the object.)
We also allow devices to define "array properties" with
DEFINE_PROP_ARRAY(): these are a way to give a device a
variable-length array of properties.
However, there is no way to define an array of link properties. If
you try to do it by passing qdev_prop_link as the arrayprop argument
to DEFINE_PROP_ARRAY() you will get a crash because qdev_prop_link
does not provide the .set and .get methods in its PropertyInfo
struct.
This patch implements a new DEFINE_PROP_LINK_ARRAY(). In
a device you can use it like this:
and in your Property array:
DEFINE_PROP_LINK_ARRAY("cpus", MyDevice, num_cpus, cpus,
TYPE_ARM_CPU, ARMCPU *),
The array property code will fill in s->num_cpus, allocate memory in
s->cpus, and populate it with pointers.
On the device-creation side you set the property in the same way as
the existing array properties, using the new qlist_append_link()
function to append to the QList:
QList *cpulist = qlist_new();
for (int i = 0; i < cpus; i++) {
qlist_append_link(cpulist, OBJECT(cpu[i]));
}
qdev_prop_set_array(mydev, "cpus", cpulist);
The implementation is mostly in the provision of the .set and
.get methods to the qdev_prop_link PropertyInfo struct. The
code of these methods parallels the code in
object_set_link_property() and object_get_link_property(). We can't
completely share the code with those functions because of differences
in where we get the information like the target QOM type, but I have
pulled out a new function object_resolve_and_typecheck() for the
shared "given a QOM path and a type, give me the object or an error"
code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260327111700.795099-3-peter.maydell@linaro.org
Peter Maydell [Fri, 27 Mar 2026 11:15:56 +0000 (11:15 +0000)]
qom/object: Add object_resolve_and_typecheck()
Add a new function object_resolve_and_typecheck(), whose purpose is
to look up the object at a given QOM path, confirm that it is the
expected type, and return it. This is similar to the existing
object_resolve_path_type(), but it insists on a non-ambiguous path.
We were already using this functionality internally to object.c as
part of the object_resolve_link() function, so this patch implements
the new function by pulling the link-property specific parts out of
the more generic resolve-and-typecheck part.
The motivation for this function is that we want to allow devices to
provide an array of link properties; for that we will need to be able
to provide the expected type of the linked object in a different way
to the single-item link properties.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260327111700.795099-2-peter.maydell@linaro.org
Stacey Son [Sat, 14 Mar 2026 17:49:02 +0000 (11:49 -0600)]
bsd-user: Add do_bsd_ioctl main function
Add main ioctl emulation dispatcher that handles table-driven
ioctl translation with thunk-based structure conversion. Supports
TYPE_NULL, TYPE_INT, and TYPE_PTR argument types with read, write,
and read-write access modes.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 17:41:00 +0000 (11:41 -0600)]
bsd-user: Add do_ioctl_in6_ifreq_sockaddr_int function
Add special handler for IPv6 interface request ioctls that take
a sockaddr_in6 structure as input and return an integer flag value,
such as SIOCGIFAFLAG_IN6 and SIOCGIFALIFETIME_IN6.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 17:32:52 +0000 (11:32 -0600)]
bsd-user: Add target_to_host_sockaddr_in6 function
Add helper function to convert target IPv6 socket address structure
to host format, handling all sockaddr_in6 fields including address,
port, flow info, and scope ID.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 17:26:01 +0000 (11:26 -0600)]
bsd-user: Add bsd-ioctl.c infrastructure and termios conversion
Add initial bsd-ioctl.c file with termios conversion functions,
structure type definitions, and ioctl table infrastructure.
Includes target_to_host_termios and host_to_target_termios for
terminal I/O control conversion, along with the ioctl dispatch
table framework.
Style complains about STRUCT and STRUCT_SPECIAL defines:
● checkpatch.pl: 197: ERROR: Macros with complex values should be enclosed in parenthesis
● checkpatch.pl: 198: ERROR: Macros with complex values should be enclosed in parenthesis
but that's fine. We are doing weird things with macros, and it's fine.
We can't put parens or do while (0) around these since they are table
building macros for files that are included multiple times.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Sean Bruno <sbruno@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 04:13:18 +0000 (22:13 -0600)]
bsd-user: Add bsd-ioctl.h header
Add bsd-ioctl.h header declaring the public ioctl emulation API:
do_bsd_ioctl() for processing ioctl system calls and init_bsd_ioctl()
for initialization.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 04:13:02 +0000 (22:13 -0600)]
bsd-user: Add FreeBSD ioctl command table
Add os-ioctl-cmds.h containing the complete ioctl command table
mapping TARGET_* ioctl commands to their handlers. Uses IOCTL and
IOCTL_SPECIAL macros for table generation.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Alexander Kabaev <kan@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 04:12:59 +0000 (22:12 -0600)]
bsd-user: Add FreeBSD ioctl type definitions
Add os-ioctl-types.h with STRUCT macro definitions for ioctl type
registration. This header uses multiple inclusion with different
STRUCT macro definitions to generate both enums and type definitions.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 04:12:53 +0000 (22:12 -0600)]
bsd-user: Add FreeBSD IPv6 ioctl definitions
Add os-ioctl-in6_var.h with IPv6 network interface ioctl definitions
including SIOCAIFADDR_IN6, SIOCDIFADDR_IN6, and related IPv6
configuration ioctls with target_in6_* structure definitions.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 04:11:56 +0000 (22:11 -0600)]
bsd-user: Add FreeBSD socket ioctl definitions
Add os-ioctl-sockio.h with network socket and interface control ioctl
definitions including SIOCGIFADDR, SIOCSIFADDR, SIOCGIFCONF, and
related network interface ioctls with target_ structure definitions.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Stacey Son [Sat, 14 Mar 2026 04:11:23 +0000 (22:11 -0600)]
bsd-user: Add FreeBSD tty ioctl definitions
Add os-ioctl-ttycom.h with terminal control ioctl definitions including
TARGET_TIOCGETA, TARGET_TIOCSETA, window size ioctls, and the
target_termios structure for terminal I/O control.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Warner Losh [Mon, 13 Apr 2026 14:39:38 +0000 (08:39 -0600)]
bsd-user: Switch to generated syscall_nr.h
Now that this will build and work, remove the old syscall_nr.h and
switch the include over to the generated file in syscall_defs.h.
To do this, I had to delete the old, wrong definition of time_t for
FreeBSD on amd64 since it stumbled over the fact that TARGET_i386 is
defined for both 32-bit and 64-bit builds (the new os-syscall.h had the
rigth definition). Rather than modify this file twice to fix it, rolled
the fix into using os-syscall.h since it's still easy enough to review.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Warner Losh [Mon, 13 Apr 2026 14:54:47 +0000 (08:54 -0600)]
bsd-user: Create os-syscall.h
Create os-syscall.h. The purpose of this file is to define anything
that's different among the BSDs, like system call numbers and
time_t. While there's a lot more different between the BSDs, this is at
least a start at capturing it.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Warner Losh [Mon, 13 Apr 2026 14:36:31 +0000 (08:36 -0600)]
bsd-user: Delete sbrk and sstk system calls.
sbrk and sstk were an experimental system call introduced in 4.2BSD, but
with an blank implementation. They remained in subsequent 4BSD releases
doing nothing (with 4.3-Reno and later returning not supported). FreeBSD
1.x imported this. They were removed in 2023. Remove them from here
because no real, non-contrived program on FreeBSD ever had them.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Warner Losh [Mon, 13 Apr 2026 14:20:40 +0000 (08:20 -0600)]
bsd-user: Add syscall header generator for FreeBSD
Generate the syscall numbers from the installed header that has them.
Ideally, we'd use FreeBSD's lua infra for this, but that requires that
we have those files installed, and they aren't quite the same across
supported versions yet, so use this simple, but effective hack. Add to
meson build, but unused.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
Warner Losh [Tue, 3 Mar 2026 03:48:22 +0000 (20:48 -0700)]
bsd-user: Switch to SPDX-License-Expression
Two minor changes to the copyright and license marking for these files:
(1) Stacey D Son is used instead of variations of his name.
(2) The GPL boilerplate is replaced by SPDX markings. No change to the
terms of the license are intended, and this matches current QEMU practice.
There's no changes to the license or additional claims to any IP that
others may hold in these files. All the S-o-bs in this commit have given
me permission to do this to the extent they may hold rights. git blame
over multiple repos and branches suggests that only minimal other
material is present (much of it likely not subject to copyright
protection). The project's long and complex history as well as tooling
limitations make it hard to be 100% sure. Any omissions are
unintentional and I will correct them as they come to light.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Sean Bruno <sbruno@FreeBSD.org> Signed-off-by: Mikaël Urankar <mikael.urankar@gmail.com> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Guy Yur <guyyur@gmail.com> Signed-off-by: Alexander Kabaev <kan@FreeBSD.org> Signed-off-by: Michal Meloun <mmel@FreeBSD.org> Signed-off-by: Ed Schouten <ed@nuxi.nl> Signed-off-by: Karim Taha <kariem.taha2.7@gmail.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
* tag 'single-binary-20260506' of https://github.com/philmd/qemu: (110 commits)
system/vl: inline qemu_opts_parse_noisily() result checks
scripts/checkpatch: Avoid false positive on empty blocks
cocci: Do not initialize variable used by RAMBLOCK_FOREACH* macro
cocci: Do not initialize variable used by QTAILQ_FOREACH macro
cocci: Do not initialize variable used by QSIMPLEQ_FOREACH macro
cocci: Do not initialize variable used by QSLIST_FOREACH macro
cocci: Do not initialize variable used by QLIST_FOREACH macro
scripts/checkpatch: Reject another license boilerplate pattern
io: use g_clear_handle_id() for GSource cleanup
io: Clear dangling GLib event source tag
target/xtensa/core: register types using type_init
target/s390x: Do not compile KVM stubs for linux-user binary
target/mips: Do not initialize variable used by CPU_FOREACH macro
target/mips: Reduce CPUState scope when used with CPU_FOREACH()
target/riscv: Iterate vCPUs using CPU_FOREACH() macro
target/s390x: Replace cpu_stb_data_ra -> cpu_stb_mmu in STFLE opcode
target/s390x: Compile crypto_helper.c as common unit
target/s390x: Have MSA helper pass a mmu_idx argument
target/s390x: Compile vec_helper.c as common unit
target/s390x: Compile translate.c as common unit
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Wed, 6 May 2026 14:31:51 +0000 (10:31 -0400)]
Merge tag 'next-pull-request' of https://gitlab.com/peterx/qemu into staging
Migration and mem pull request
- Fabiano's fix on migrate_set_parameter crash with multifd & zerocopy
- Pranav's fix on postcopy stucking at device state when ack lost
- Samuel's new migration parameter x-rdma-chunk-size for RDMA
- PeterX's vfio/migration series to report remaining data and fix downtime calc
- PeterM's MemoryRegionOps .impl cleanup series
- Fabiano's fix to build a-b migration bootfiles for all archs
* tag 'next-pull-request' of https://gitlab.com/peterx/qemu: (23 commits)
tests/qtest/migration: Fix A-B file build
system/memory: assert on invalid MemoryRegionOps .unaligned combo
hw/xtensa/mx_pic: Specify xtensa_mx_pic_ops .impl settings
hw/npcm7xx_fiu: Specify .impl for npcm7xx_fiu_flash_ops
hw/riscv: iommu-trap: remove .impl.unaligned = true
vfio/migration: Add tracepoints for precopy/stopcopy query ioctls
migration/qapi: Update unit for avail-switchover-bandwidth
migration/qapi: Introduce system-wide "remaining" reports
migration: Remember total dirty bytes in mig_stats
migration: Fix calculation of expected_downtime to take VFIO info
migration: Calculate expected downtime on demand
migration: Introduce a helper to return switchover bw estimate
migration: Move iteration counter out of RAM
vfio/migration: Fix incorrect reporting for VFIO pending data
migration: Introduce stopcopy_bytes in save_query_pending()
migration: Use the new save_query_pending() API directly
migration/treewide: Merge @state_pending_{exact|estimate} APIs
vfio/migration: Cache stop size in VFIOMigration
migration/qapi: Rename MigrationStats to MigrationRAMStats
migration: Fix low possibility downtime violation
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Wed, 6 May 2026 14:30:03 +0000 (10:30 -0400)]
Merge tag 'or1k-maint-20260505' of https://github.com/stffrdhrn/qemu into staging
OpenRISC board maintainer updates for 2026-05-05
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmn6JL0ACgkQw7McLV5m
# J+TQGg//bqg5NQQP9VdM6EHqeHsy8RykKFotHU6hNDML+Gj5+4mnUvqLFwZBR9Rr
# AWizrCl9wHvP/RGDSZuM9QWSVsN3CUni60R5KIV/vkwEUTRhnRReHukYmGKItHbO
# pI+8KcYfD1/nflDXvAgtz+YaDLGruIUIvL651OMElAYoDrQxN+x4XilPHQRRNLfo
# ugJjHXaikXBLFwoEhEHzbNK8qeEtJQyN7GHOyigy+R5vrfBqqXYwNZQBUI/9rUrk
# VHKo9G25BjxgJC7mvBRJynzVpIu8McX9xqc4HmNepR4D9WCtR7Cndsh7cRPTgyju
# r5CjLvZahuzqdM/xluyMrApQQ8Qe4yChdNCsxhue83KZdOriGFzwz8aPyXKllMw3
# S7UyVkf1ZL1Th+Z4lBSzu+w2+5+Lz6xyQdUjUF9HR8x7QXD7Ouuofo+aUHweU2/N
# mnZvSvUa/zaq/ixUiHq21uqKASQxtIsF0aD5TGKIpYbWX181VpC1Xjh7KgmikzUF
# Yu93PvqvYN4KlzXU9o4uGuP4TmmI0AUSzGLrjTWCjWUwXOUYPwcWWxqAFZEIZToE
# MTIaWrvw5avzZI+CLuC3ZS9MJ+wpp/96QiUt7JJRI1PBO/Odf3SyQ+iu4F1dMSCp
# 6vRu9kj7+mjfW1avkUP4AzoVaD+DfKzNGtSJ1PqcC9e3rFVjqog=
# =uEyH
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 05 May 2026 13:11:25 EDT
# gpg: using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4
* tag 'or1k-maint-20260505' of https://github.com/stffrdhrn/qemu:
MAINTAINERS: Add myself as the OpenRISC virt maintainer
MAINTAINERS: Add myself as maintainer for or1k-sim
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Bin Guo [Wed, 29 Apr 2026 06:20:04 +0000 (14:20 +0800)]
system/vl: inline qemu_opts_parse_noisily() result checks
In qemu_init()'s option parsing switch, several cases assigned the
return value of qemu_opts_parse_noisily() to the shared 'opts'
variable solely to check for NULL, without using the pointer
afterwards. Inline the call directly into the if-condition, matching
the style already used by QEMU_OPTION_action.
This affects the following options:
-drive, -numa, -iscsi, -m, -mon, -chardev, -fsdev, -fwcfg
Cases where the returned QemuOpts* is subsequently used (e.g.
-acpitable, -smbios, -virtfs) are left unchanged.
Signed-off-by: Bin Guo <guobin@linux.alibaba.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260429062004.36582-4-guobin@linux.alibaba.com>
[PMD: Reduce @opts declaration to innermost block] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
scripts/checkpatch: Avoid false positive on empty blocks
SUSPECT_CODE_INDENT checks the first line after a conditional statement.
When the block is empty, the first line after the conditional is the
closing brace at the same indentation level, so checkpatch reports a
bogus indentation error.
Ignore same-indented braces and else statements, matching with:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f6950a735f29e782bc219ece22bb91d6e1ab7bbc
Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Message-ID: <20260424-force_rcu-v4-6-feccfaca0568@rsg.ci.i.u-tokyo.ac.jp> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
cocci: Do not initialize variable used by RAMBLOCK_FOREACH* macro
The RAMBLOCK_FOREACH_MIGRATABLE() macro, defined in
migration/ram.h, ends up calling QLIST_FOREACH_RCU()
which always assigns its iterator variable when entering
the loop. Remove the pointless and possibly misleading
assignment.
Mechanical patch using the following coccinelle spatch:
@@
type T;
identifier e;
iterator FOREACH_MACRO =~ ".*_FOREACH.*";
statement S;
@@
- T *e = ...;
+ T *e;
... when != e
FOREACH_MACRO(e, ...) S
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260415215539.92629-6-philmd@linaro.org>
cocci: Do not initialize variable used by QTAILQ_FOREACH macro
The QTAILQ_FOREACH() macro, defined in "qemu/queue.h",
always assigns its iterator variable when entering the
loop. Remove the pointless and possibly misleading
assignment.
Mechanical patch using the following coccinelle spatch:
@@
type T;
identifier e;
iterator FOREACH_MACRO =~ ".*_FOREACH.*";
statement S;
@@
- T *e = ...;
+ T *e;
... when != e
FOREACH_MACRO(e, ...) S
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260415215539.92629-5-philmd@linaro.org>
cocci: Do not initialize variable used by QSIMPLEQ_FOREACH macro
The QSIMPLEQ_FOREACH() macro, defined in "qemu/queue.h",
always assigns its iterator variable when entering the
loop. Remove the pointless and possibly misleading
assignment.
Mechanical patch using the following coccinelle spatch:
@@
type T;
identifier e;
iterator FOREACH_MACRO =~ ".*_FOREACH.*";
statement S;
@@
- T *e = ...;
+ T *e;
... when != e
FOREACH_MACRO(e, ...) S
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260415215539.92629-4-philmd@linaro.org>
cocci: Do not initialize variable used by QSLIST_FOREACH macro
The QSLIST_FOREACH() macro, defined in "qemu/queue.h",
always assigns its iterator variable when entering the
loop. Remove the pointless and possibly misleading
assignment.
Mechanical patch using the following coccinelle spatch:
@@
type T;
identifier e;
iterator FOREACH_MACRO =~ ".*_FOREACH.*";
statement S;
@@
- T *e = ...;
+ T *e;
... when != e
FOREACH_MACRO(e, ...) S
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260415215539.92629-3-philmd@linaro.org>
cocci: Do not initialize variable used by QLIST_FOREACH macro
The QLIST_FOREACH() macro, defined in "qemu/queue.h",
always assigns its iterator variable when entering the
loop. Remove the pointless and possibly misleading
assignment.
Mechanical patch using the following coccinelle spatch:
@@
type T;
identifier e;
iterator FOREACH_MACRO =~ ".*_FOREACH.*";
statement S;
@@
- T *e = ...;
+ T *e;
... when != e
FOREACH_MACRO(e, ...) S
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260415215539.92629-2-philmd@linaro.org>
Bernhard Beschow [Tue, 14 Apr 2026 13:50:18 +0000 (15:50 +0200)]
scripts/checkpatch: Reject another license boilerplate pattern
The pattern us used 56 times in QEMU.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Tested-by: Matyas Bobek <matyas.bobek@gmail.com>
Message-ID: <20260414135018.13585-1-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Use g_clear_handle_id() instead of g_source_remove() with
manual ID checking and zeroing.
This simplifies the code and ensures consistent handling of
GSource IDs, since g_clear_handle_id() checks for a non-zero
ID before calling the cleanup function and zeros it afterwards.
No functional change intended.
Mechanical change using the following Coccinelle spatch script:
@@
expression TAG;
@@
- if (TAG > 0) {
+ if (TAG) {
g_source_remove(TAG);
<... when != TAG
TAG = 0;
...>
}
Inspired-by: Matthew Penney <matt@matthewpenney.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Matthew Penney <matt@matthewpenney.net>
Message-Id: <20260408100605.66795-3-philmd@linaro.org>
Following commit 34aad589019 ("hw/char/virtio-console: clear
dangling GLib event source tag"), prevent stale tags from
being reused by clearing dangling GLib event source tag during
the cleanup phase (finalize, unrealize).
Inspired-by: Matthew Penney <matt@matthewpenney.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Matthew Penney <matt@matthewpenney.net>
Message-Id: <20260408100605.66795-2-philmd@linaro.org>
target/xtensa/core: register types using type_init
Instead of using a static constructor, delay registering those types
until we call module_init(MODULE_INIT_QOM).
This is not yet a problem, but since we will start initializing
target-info types before any other, without this patch
qemu-system-xtensa* fails with:
Type 'dsp3400-xtensa-cpu' is missing its parent 'xtensa-cpu'
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-ID: <20260430203842.29156-4-pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/mips: Do not initialize variable used by CPU_FOREACH macro
The CPU_FOREACH() macro, defined in "hw/core/cpu.h",
ends up calling QTAILQ_FOREACH_RCU() which always
assigns its iterator variable when entering the loop.
Remove the pointless and possibly misleading assignment.
Mechanical patch using the following coccinelle spatch:
@@
type T;
identifier e;
iterator FOREACH_MACRO =~ ".*_FOREACH.*";
statement S;
@@
- T *e = ...;
+ T *e;
... when != e
FOREACH_MACRO(e, ...) S
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260415215539.92629-7-philmd@linaro.org>
target/s390x: Replace cpu_stb_data_ra -> cpu_stb_mmu in STFLE opcode
In preparation of building misc_helper.c as a common unit, update
the cpu_ld/st_be_data_ra() API by cpu_ld/st_mmu() one and replace
"accel/tcg/cpu-ldst.h" by "accel/tcg/cpu-ldst-common.h".
For now we are blocked by the CONFIG_DEVICES use so keep the file
in s390x_ss[].
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20260423135035.50126-10-philmd@linaro.org>
target/s390x: Have MSA helper pass a mmu_idx argument
Next commit will use the cpu_ld/st_mmu() API and thus
will also use a @mmu_idx. In order to keep it simple to
review, propate @mmu_idx in a preliminary step.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20260423135035.50126-8-philmd@linaro.org>
target/s390x: Introduce common system/user meson source set
Introduce a source set common to system / user. Start it
with the files built in both sets: 'cpu_models_user.c'
and 'gdbstub.c' No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20260423135035.50126-4-philmd@linaro.org>
target/microblaze: Include missing cpu-mmu-index.h header in translate.c
translate.c calls cpu_mmu_index(), itself defined in
"accel/tcg/cpu-mmu-index.h". This header is pulled in
indirectly via "accel/tcg/cpu-ldst.h", but since we'll
remove the latter in the next commit, make the inclusion
explicit, otherwise we'd get:
../target/microblaze/translate.c:1620:21: error: call to undeclared function 'cpu_mmu_index'
1620 | dc->mem_index = cpu_mmu_index(cs, false);
| ^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260423100612.27278-9-philmd@linaro.org>
In preparation of removing the translator_ld[uw,l,q]() methods,
inline them for the microblaze targets, using mo_endian(ctx) --
which we introduced in commit 2c9e8ddd7699 -- instead of MO_TE.
Remove mb_cpu_is_big_endian() which is now unused.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260423100612.27278-4-philmd@linaro.org>
target/microblaze: Fix endianness used to disassemble
MicroBlaze CPU model has a "little-endian" property, pointing to
the @endi internal field. Commit c36ec3a9655 ("hw/microblaze:
Explicit CPU endianness") took care of having all MicroBlaze
boards with an explicit default endianness (similarly with
commit 91fc6d8101d for linux-user binaries), so later commit 415aae543ed ("target/microblaze: Consider endianness while
translating code") could infer the endianness at runtime from
the @endi field, and not a compile time via the TARGET_BIG_ENDIAN
definition. Doing so, we forgot to propagate that runtime change
to the disassemble_info structure. Do it now to display the
opcodes in correct endianness order.
Cc: qemu-stable@nongnu.org Fixes: 415aae543ed ("target/microblaze: Consider endianness while translating code") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260423100612.27278-3-philmd@linaro.org>
We use the mechanic introduced in previous commit to define a arm stubs
library. With this, we are able to eliminate symbol conflicts when
linking arm and aarch64 targets, and get one step closer to having a
single-binary.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20260424230103.1579600-3-pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
tcg: Include missing 'tcg/tcg-op-common.h' header in 'tcg-op-mem.h'
"tcg-op-mem.h" uses methods declared in "tcg/tcg-op-common.h".
Include the latter to avoid when including the former:
include/tcg/tcg-op-mem.h:34:5: error: call to undeclared function 'tcg_gen_qemu_ld_i32_chk'
34 | tcg_gen_qemu_ld_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA);
| ^
meson.build: define stubs library per target base architecture
QEMU stubs (from stubs folder) have a unique feature: they emulate weak
symbols. Weak symbols are not supported on Windows with gcc. This is
achieved by defining a static library, so the linker can pick a file
only when one of its symbol is needed.
The problem is that common stubs are embedded in qemuutil, which is
defined and created before any target code. Thus, to benefit from the
same feature for target code, we need to create stub static libraries
for each target architecture.
To keep things simple, we declare one library per target base
architecture. This implies that stubs are compiled only once, and we
choose them to be system common files. This is not a big issue, since
stubs definition have no specific behaviour, out of returning a default
value, or stopping execution, which makes this safe to link them in user
binaries also.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20260424230103.1579600-2-pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
meson: Allow building with empty target_arch[] source set
Complete commit 83d5db95d38 ("meson: Allow system binaries
to not have target-specific units") with yet another guard,
allowing empty target_arch[] source sets for some targets.
Unfortunately commit 54821ff6e90 ("target/mips: Convert mips16e
decr_and_load/store() macros to functions") got rebased on top
of commit 2803e24694c ("target/mips: Replace MO_TE by mo_endian")
and we missed the replacement. Fix that.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260417042620.35329-5-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260417042620.35329-4-philmd@linaro.org>
target/mips: Inline cpu_ld/st_mmuidx_ra() calls in Atomic LD/ST helpers
Have callers set MO_ALIGN in the MemOp bits.
Perform the access first, filling the TLB in the process.
If the tlb cannot be filled, access is not permitted, and
an exception is raised. Thus remove the now unnecessary
do_raise_exception() call.
Since the TLB is filled, use probe_access() to get CP0_LLAddr.
Move env->CP0_LLAddr and env->lladdr assignments so we
don't update them when an alignment fault occurs.
Since we have a handy MemOpIdx, replace the legacy
cpu_ld*_mmuidx_ra() calls by cpu_ld*_mmu() equivalent.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260417042620.35329-3-philmd@linaro.org>
target/mips: Pass MemOpIdx argument to Linked Load/Store helpers
In preparation of using the MemOp content in the next commit
(thus stopping ignoring it), pass it as MemOpIdx.
The helper prototype declaration always took a TCGv_i32 as
last argument, correct that.
Rename the ignored 'mem_idx' argument on user emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260417042620.35329-2-philmd@linaro.org>
target/mips: Expand TCGv type for 64-bit extensions
These TX79, Octeon and Loongarch extensions are only built
as 64-bit, so TCGv expands to TCGv_i64. Use the latter which
is more explicit. Mechanical changes.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20260401144503.80510-3-philmd@linaro.org>
All uses were converted to the cpu_ld*_code_mmu() helpers:
remove them. Update the documentation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260320074555.33974-3-philmd@linaro.org>
target/mips: Inline cpu_ld{uw,l}_code() calls in set_badinstr_registers
In preparation of removing the cpu_lduw_code() and cpu_ldl_code()
wrappers, inline them. Directly replace MO_TE by mo_endian_env(env).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260320074555.33974-2-philmd@linaro.org>
When converting 'info pic' to QMP in commit 795eaa62fa6 ("hw/intc:
Introduce x-query-interrupt-controllers QMP command"), we forgot
to remove the hmp_info_pic() declaration. Do it now.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-33-philmd@linaro.org>
monitor: Merge hmp-target.c code within hmp-cmds.c
hmp-target.c doesn't contain any target-specific code anymore.
Merge it within hmp-cmds.c (which is already built once).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-32-philmd@linaro.org>
target_monitor_defs() is now only a dead stub. Remove as pointless.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-31-philmd@linaro.org>
Restrict sparc64_monitor_defs[] to cpu.c, register it
as SysemuCPUOps::monitor_defs hook (taking care to not
register it on 32-bit SPARC target), allowing to remove
the target_monitor_defs() method.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-30-philmd@linaro.org>
Restrict m68k_monitor_defs[] to cpu.c, register it as
SysemuCPUOps::monitor_defs hook, allowing to remove
the target_monitor_defs() method.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-29-philmd@linaro.org>
Restrict x86_monitor_defs[] to cpu.c, register it as
SysemuCPUOps::monitor_defs hook, allowing to remove
the target_monitor_defs() method.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-28-philmd@linaro.org>
Allow targets to register their legacy target_monitor_defs()
in SysemuCPUOps; check it first in get_monitor_def() otherwise
fall back to previous per-target helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-27-philmd@linaro.org>
Rather than having core header forced to include "monitor/hmp.h"
to get the MonitorDef type declaration, forward-declare it in
"qemu/typedefs.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-26-philmd@linaro.org>
The "monitor/hmp-target.h" header doesn't contain any
target-specific declarations anymore. Merge it with
"monitor/hmp.h", its target-agnostic counterpart.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20260427080738.77138-25-philmd@linaro.org>
get_monitor_def() doesn't use any target-specific declaration
anymore, move it to hmp.c to compile it once.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20260427080738.77138-24-philmd@linaro.org>
target_get_monitor_def() is now only a dead stub. Remove as pointless.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-22-philmd@linaro.org>
target/riscv: Register target_get_monitor_def in SysemuCPUOps
Rename target_get_monitor_def() as riscv_monitor_get_register_legacy()
and register it as SysemuCPUOps::monitor_get_register() handler.
Take care to sign-extend values for 32-bit HARTs.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260427080738.77138-21-philmd@linaro.org>
Allow targets to register their legacy target_get_monitor_def()
in SysemuCPUOps; check it first in get_monitor_def() otherwise
fall back to previous per-target helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-20-philmd@linaro.org>
monitor: Do not check multiple TARGET_* to build 'info tlb' command
This command is filtered at build-time for a selection of binaries.
By using the recently introduced HMPCommand::arch_bitmask flag we
can filter them at runtime, making it possible to compile
hmp-commands-info.hx once.
Since the method depends on a pair of distinct targets,
define it in its own stub file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260427080738.77138-19-philmd@linaro.org>
monitor: Do not check TARGET_I386/RISCV to build 'info mem' command
This command is filtered at build-time for i386/x86_64 and
riscv32/riscv64 binaries. By using the recently introduced
HMPCommand::arch_bitmask flag we can filter it at runtime,
making it possible to compile hmp-commands-info.hx once.
Since the method depends on a pair of distinct targets,
define it in its own stub file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260427080738.77138-18-philmd@linaro.org>
projects / thirdparty / qemu.git / log
