Sean Anderson [Wed, 8 Nov 2023 16:48:34 +0000 (11:48 -0500)]
arm: Disable SPL_FS_FAT when it isn't used
Several boards enable SPL_FS_FAT and SPL_LIBDISK_SUPPORT when they can't be
used (as there is no block device support enabled). Disable these configs.
The list of boards was generated with the following command:
LIBDISK was left enabled for the am* boards, since it seems to result in
actual size reduction, indicating that partitions are being used for
something.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michal Simek <michal.simek@amd.com>
Sean Anderson [Wed, 8 Nov 2023 16:48:33 +0000 (11:48 -0500)]
spl: blk_fs: Fix uninitialized return value when we can't get a blk_desc
Initialize ret to avoid returning garbage if blk_get_devnum_by_uclass_id
fails.
Fixes: 8ce6a2e1757 ("spl: blk: Support loading images from fs") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sun, 5 Nov 2023 02:27:42 +0000 (22:27 -0400)]
arm: Enable SYS_THUMB_BUILD on AT91
Several AT91 boards are quite close to their SPL size limit. For example,
sama5d27_wlsom1_ek_mmc is just 173 bytes short of its limit and doesn't
even fit with older GCCs.
All AT91 processors should have thumb support. Enable SYS_THUMB_BUILD. This
shrinks SPL by around 30%.
Sean Anderson [Sat, 4 Nov 2023 20:37:53 +0000 (16:37 -0400)]
test: spl: Add a test for NAND
Add a SPL test for the NAND load method. We use some different functions to
do the writing from the main test since things like nand_write_skip_bad
aren't available in SPL.
We disable BBT scanning, since scan_bbt is only populated when not in SPL.
We use nand_spl_loaders.c as it seems to be common to at least a few boards
already. However, we do not use nand_spl_simple.c because it would require
us to implement cmd_ctrl. The various nand load functions are adapted from
omap_gpmc. However, they have been modified for simplicity/correctness.
Sean Anderson [Sat, 4 Nov 2023 20:37:52 +0000 (16:37 -0400)]
nand: Add sandbox driver
Add a sandbox NAND flash driver to facilitate testing. This driver supports
any number of devices, each using a single chip-select. The OOB data is
stored in-band, with the separation enforced through the API.
For now, create two devices to test with. The first is a very small device
with basic ECC. The second is an 8G device (chosen to be larger than 32
bits). It uses ONFI, with the values copied from the datasheet. It also
doesn't need too strong ECC, which speeds things up.
Although the nand subsystem determines the parameters of a chip based on
the ID, the driver itself requires devicetree properties for each
parameter. We do not derive parameters from the ID because parsing the ID
is non-trivial. We do not just use the parameters that the nand subsystem
has calculated since that is something we should be testing. An exception
is made for the ECC layout, since that is difficult to encode in the device
tree and is not a property of the device itself.
Despite using file I/O to access the backing data, we do not support using
external files. In my experience, these are unnecessary for testing since
tests can generally be written to write their expected data beforehand.
Additionally, we would need to store the "programmed" information somewhere
(complicating the format and the programming process) or try to detect
whether block are erased at runtime (degrading probe speeds).
Information about whether each page has been programmed is stored in an
in-memory buffer. To simplify the implementation, we only support a single
program per erase. While this is accurate for many larger flashes, some
smaller flashes (512 byte) support multiple programs and/or subpage
programs. Support for this could be added later as I believe some
filesystems expect this.
To test ECC, we support error-injection. Surprisingly, only ECC bytes in
the OOB area are protected, even though all bytes are equally susceptible
to error. Because of this, we take care to only corrupt ECC bytes.
Similarly, because ECC covers "steps" and not the whole page, we must take
care to corrupt data in the same way.
Sean Anderson [Sat, 4 Nov 2023 20:37:51 +0000 (16:37 -0400)]
arch: sandbox: Add function to create temporary files
When working with sparse data buffers that may be larger than the address
space, it is convenient to work with files instead. Add a function to create
temporary files of a certain size.
Sean Anderson [Sat, 4 Nov 2023 20:37:49 +0000 (16:37 -0400)]
nand: Add function to unregister NAND devices
This performs the opposite of nand_register, allowing drivers to unregister
nand devices. This is probably unnecessary for most regular drivers, but we
expect sandbox drivers to get repeatedly bound/unbound, so this will help
avoid dangling pointers.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Sean Anderson [Sat, 4 Nov 2023 20:37:44 +0000 (16:37 -0400)]
spl: nand: Set bl_len to page size
Since commit 34793598c83 ("mtd: nand: mxs_nand_spl: Remove the page aligned
access") there are no longer any users of nand_get_mtd. However, it is
still important to know what the page size is so we can allocate a
large-enough buffer. If the image size is not page-aligned, we will go off
the end of the buffer and clobber some memory.
Introduce a new function nand_page_size which returns the page size. For
most drivers it is easy to determine the page size. However, a few need to
be modified since they only keep the page size around temporarily.
It's possible that this patch could cause a regression on some platforms if
the offset is non-aligned and there is invalid address space immediately
before the load address. spl_load_legacy_img does not (except when
compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or
SPL_LOAD_IMX_CONTAINER (none in tree) would be affected.
All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q
which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the
i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a
little underflow.
Sean Anderson [Sat, 4 Nov 2023 20:37:43 +0000 (16:37 -0400)]
spl: legacy: Honor bl_len when decompressing
When allocating a buffer to load compressed data into, we need to ensure we
have enough space for over- and under-flow due to alignment. Otherwise we
will clobber the malloc bookkeeping data. Calculate the correct amount of
overhead and use it when determining the size.
Sean Anderson [Sat, 4 Nov 2023 20:37:42 +0000 (16:37 -0400)]
nand: spl_loaders: Only read enough pages to load the image
All other implementations of nand_spl_load_image only read as many pages as
are necessary to load the image. However, nand_spl_loaders.c loads the full
block. Align it with other load functions so that it is easier to
determine how large of a load buffer we need.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Contrary to what the help message says, this is the number of pages per
block. Calculate it automatically based on SYS_NAND_BLOCK_SIZE and
SYS_NAND_PAGE_SIZE. To better reflect its semantics, rename it to
SYS_NAND_BLOCK_PAGES.
Sean Anderson [Sat, 4 Nov 2023 20:37:40 +0000 (16:37 -0400)]
nand: Don't dereference NULL manufacturer_desc
When no manufacturer is matched, manufacturer_desc is NULL. Avoid
dereferencing it in that case.
Fixes: 4e67c571252 ("mtd,ubi,ubifs: sync with linux v3.15") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Simon Glass [Tue, 7 Nov 2023 09:17:40 +0000 (10:17 +0100)]
bootstage: Correct exhasuted typo
Correct this typo in the warning message shown when no more bootstage
records can be added.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 4 Nov 2023 19:57:33 +0000 (15:57 -0400)]
sandbox: Close file after mmaping it
After opening pathname, we must close ifd once we are done with it.
Fixes: b9274095c2c ("sandbox: Add a way to map a file into memory") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
CONFIG_DM_WARN has a text indicating that these messages should only
provided when debugging. This implies that the setting must be default no.
We should still create debug messages.
Reported-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 4 Nov 2023 16:25:24 +0000 (10:25 -0600)]
patman: Correct Python 3.6 behaviour
The importlib_resources import is not actually used. Fix this so that
patman can run on Python 3.6 to some extent, once
'pip3 install importlib-resources' has been run.
Simon Glass [Mon, 2 Oct 2023 01:14:37 +0000 (19:14 -0600)]
bootstd: Refactor mmc prep to allow a different scan
Adjust scan_mmc4_bootdev() and related function so that the caller can
do its own 'bootflow scan' command. This allows it to change the flags
if needed.
Simon Glass [Mon, 2 Oct 2023 01:14:36 +0000 (19:14 -0600)]
efi: Correct handling of frame buffer
The efi_gop driver uses private fields from the video uclass to obtain a
pointer to the frame buffer. Use the platform data instead.
Check the VIDEO_COPY setting to determine which frame buffer to use. Once
the next stage is running (and making use of U-Boot's EFI boot services)
U-Boot does not handle copying from priv->fb to the hardware framebuffer,
so we must allow EFI to write directly to the hardware framebuffer.
We could provide a function to read this, but it seems better to just
document how it works. The original change ignored an explicit comment
in the video.h file ("Things that are private to the uclass: don't use
these in the driver") which is why this was missed when the VIDEO_COPY
feature was added.
Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 8f661a5b662 ("efi_loader: gop: Expose fb when 32bpp") Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Patrice Chotard [Fri, 27 Oct 2023 14:43:04 +0000 (16:43 +0200)]
stm32mp2: initial support
Add initial support for STM32MP2 SoCs family.
SoCs information are available here :
https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html
Migrate all MP1 related code into stm32mp1/ directory
Create stm32mp2 directory dedicated for STM32MP2 SoCs.
Common code to MP1, MP13 and MP25 is kept into
arch/arm/mach-stm32/mach-stm32mp directory :
- boot_params.c
- bsec
- cmd_stm32key
- cmd_stm32prog
- dram_init.c
- syscon.c
- ecdsa_romapi.c
For STM32MP2, it also :
- adds memory region description needed for ARMv8 MMU.
- enables early data cache before relocation.
During the transition before/after relocation, the MMU, initially setup
at the beginning of DDR, must be setup again at a correct address after
relocation. This is done in enables_caches() by disabling cache, force
arch.tlb_fillptr to NULL which will force the MMU to be setup again but
with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been
updated after relocation in arm_reserve_mmu().
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Fri, 27 Oct 2023 14:43:03 +0000 (16:43 +0200)]
ARM: dts: stm32: Add STM32MP257F Evaluation board support
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC,
with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC,
SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Sync device tree with kernel v6.6-rc1.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
When building with AARCH64 defconfig, we got warnings for debug
message
- format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'size_t' {aka 'long unsigned int'}).
- format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'phys_addr_t' {aka 'long long unsigned
int'}
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Fri, 27 Oct 2023 14:42:56 +0000 (16:42 +0200)]
arm: caches: Make DCACHE_DEFAULT_OPTION accessible for ARM64 arch
This fixes the following compilation error in ARM64:
arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’:
arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function)
59 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
| ^~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Sam Protsenko [Tue, 7 Nov 2023 21:22:00 +0000 (15:22 -0600)]
clk: exynos: Add header guard for clk-pll.h
The clk-pll.h is going to be included in multiple files soon. Add
missing header guard to prevent possible build errors in future.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Fixes: 166097e87753 ("clk: exynos: add clock driver for Exynos7420 Soc") Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
clk_get_by_index() returns negative number on error. Assigning it to
unsigned int makes the subsequent "ret < 0" check always false, leading
in turn to possible unhandled errors. Change 'ret' variable type to
signed int so the code checks and handles clk_get_by_index() return code
properly.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Fixes: cf75cdf96ef2 ("serial: s5p: use clock api to get clock rate") Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Mon, 30 Oct 2023 16:55:02 +0000 (11:55 -0500)]
exynos: Avoid duplicate reset_cpu with SYSRESET enabled
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the exynos soc code. Fix the build with
SYSRESET enabled by omitting the function from the soc code in that
case. The code still needs to be kept around for use in SPL.
This commit was inspired by commit 6e19dc84c14b ("sunxi: Avoid duplicate
reset_cpu with SYSRESET enabled").
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Fri, 20 Oct 2023 21:46:33 +0000 (16:46 -0500)]
watchdog: s5p_wdt: Include missing CPU header
s5p watchdog driver calls samsung_get_base_watchdog() function, but its
prototype is not included. That might lead to build warnings like this:
drivers/watchdog/s5p_wdt.c: In function 'wdt_stop':
drivers/watchdog/s5p_wdt.c:16:26:
warning: implicit declaration of function
'samsung_get_base_watchdog' [-Wimplicit-function-declaration]
16 | (struct s5p_watchdog *)samsung_get_base_watchdog();
| ^~~~~~~~~~~~~~~~~~~~~~~~~
Include asm/arch/cpu.h to fix that issue.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Fri, 20 Oct 2023 21:46:32 +0000 (16:46 -0500)]
arm: exynos: Include missing CPU header in gpio.h
arch/arm/include/asm/arch/gpio.h relies on definitions from cpu.h.
Include it explicitly in gpio.h. Otherwise next build error may occur:
In file included from ./arch/arm/include/asm/gpio.h:7,
from include/cros_ec.h:14,
from board/samsung/common/board.c:8:
./arch/arm/include/asm/arch/gpio.h:1357:4:
error: 'EXYNOS4_GPIO_PART1_BASE' undeclared here
(not in a function); did you mean 'EXYNOS4_GPIO_MAX_PORT'?
1357 | { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
| ^~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Marek Vasut [Sun, 5 Nov 2023 22:42:45 +0000 (23:42 +0100)]
mmc: renesas-sdhi: Disable clock after tuning reset when possible
Currently the renesas_sdhi_reset_tuning() unconditionally leaves SDHI
clock enabled after the tuning reset. This is not always necessary.
After the driver performed tuning reset at the end of probe function,
or in the unlikely case that tuning failed during regular operation,
the SDHI clock can be disabled after the tuning reset. The following
set_ios call would reconfigure the clock as needed.
In case of regular set_ios call which requires a tuning reset, keep
the clock enabled or disabled according to the mmc->clk_disable state.
With this in place, the controllers which have not been accessed via
block subsystem after boot are left in quiescent state. However, if an
MMC device is used e.g. for environment storage, that controller would
be accessed during the environment load and left active, including its
clock which would still be generated. This is due to the design of the
MMC subsystem, which does not deinit a controller after it was started
once, the controller is only deinited in case of mmc rescan, or before
OS boot.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> Tested-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Thuan Nguyen Hong <thuan.nguyen-hong@banvien.com.vn>
Tom Rini [Sun, 12 Nov 2023 21:36:22 +0000 (16:36 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
To quote Andre:
The first few patches are some easy refactorings and fixes, most of them
actually don't change the generated binaries at all. Then there is a
defconfig for a new board, for which we just gained the .dts file from
the last kernel DT sync.
On top there is support for a new PMIC (AXP313), and LPDDR4 support for
the Allwinner H616 SoC, both of which are needed to support new devices
that appeared lately, especially cheap TV boxes.
While those are technically new features, they don't affect existing
boards, for instance the LPDDR4 support code is guarded by a new DRAM
type Kconfig variable. So the risk for regressions is very slim.
Gitlab CI passed, and I booted that briefly on some boards, including an
H616 and an H618 one (with LPDDR4).
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the NOR SPI from the Orangepi Zero 3 4GB.
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Tested-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com>
The original H616 DDR3 ODT configuration code wrote board specific values
into a sequence of paired registers.
For LPDDR3 support we needed to special-case one group of registers,
because for that DRAM type we need to write 0 into the lower register of
each pair. That already made the code less readable.
LPDDR4 support will make things even messier, so let's refactor that
code now: We allow to write different values into the lower and upper
half of each pair. The masking is moved into a macro, and use in each
write statement.
The effect is not as obvious yet, as we don't need the full flexibility at
the moment, but the motivation will become clearer with LPDDR4 support.
Andre Przywara [Sun, 30 Jul 2023 00:11:01 +0000 (01:11 +0100)]
power: pmic: sunxi: add AXP313 SPL driver
On boards using the AXP313 PMIC, the DRAM rail is often not setup
correctly at reset time, so we have to program the PMIC very early in
the SPL, before running the DRAM initialisation.
Add a simple AXP313 PMIC driver that knows about DCDC2(CPU) and
DCDC3(DRAM), so that we can bump up the voltage before the DRAM init.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Samuel Holland [Tue, 31 Oct 2023 04:57:40 +0000 (23:57 -0500)]
pinctrl: sunxi: Avoid using .bss for SPL
sunxi platforms put .bss in DRAM, so .bss is not available in SPL before
DRAM controller initialization. Therefore, this buffer must be placed in
the .data section.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Tue, 31 Oct 2023 05:22:35 +0000 (00:22 -0500)]
sunxi: mmc: Move header to the driver directory
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.
Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were changed.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Mon, 17 Jul 2023 19:29:20 +0000 (15:29 -0400)]
arm: sunxi: Correct warning in board_fit_config_name_match
When building this with clang, we get a warning about having excess
parenthesis here, or that we're incorrectly using "==" when we want "=".
Correct these by using the common size macro.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
[Andre: Use SZ_512M as per Simon's suggestion] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 27 Jun 2021 00:13:09 +0000 (01:13 +0100)]
sunxi: board: simplify early PMIC setup conditions
So far we have a convoluted #ifdef mesh that guards the early AXP PMIC
setup in board.c. That combination of &&, || and negations is very hard
to read, maintain and especially to extend.
Fortunately we have those same conditions already modelled in the
Kconfig file, so they are actually redundant. On top of that the real
reason we have those preprocessor guards in the first place is about the
symbols that are *conditionally* defined: without #ifdefs the build
would break because of them being undefined for many boards.
To simplify this, just change the guards to actually look at the symbols
needed, so CONFIG_AXP_xxx_VOLT instead of CONFIG_AXPyyy_POWER.
This drastically improves the readability of this code, and makes adding
PMIC support a pure Kconfig matter.
Doing this revealed one bug in Kconfig: there is no axp_set_dcdc4() for
the AXP818, even though CONFIG_AXP_DCDC4_VOLT includes that PMIC.
Since the AXP818 wasn't included when calling axp_set_dcdc4() in board.c,
this wasn't an issue, but becomes one now, so also remove the AXP818 from
the DCDC4 Kconfig symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Milan P. Stanić [Sat, 4 Nov 2023 14:38:15 +0000 (15:38 +0100)]
doc: build: fix wrongly written targests instead of targets
Signed-off-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Nishanth Menon [Wed, 1 Nov 2023 14:50:25 +0000 (09:50 -0500)]
doc: ti: j7200_evm: Fix OPTEE platform name
k3-j7200 does not exist in upstream OPTEE. Use j721e as the platform
name. Using k3-j7200 as OPTEE name results in broken boot due to wrong
configuration being picked.
Dylan Corrales [Sat, 28 Oct 2023 09:46:39 +0000 (05:46 -0400)]
hikey960: Fix 404 links
The build instructions for the hikey960 had some broken links. Update
the links to use new vendor URLs. Also change build instructions to
reference a different file name.
Tom Rini [Fri, 10 Nov 2023 20:25:47 +0000 (15:25 -0500)]
Merge patch series "arm: dts: k3-am6: Fix Ethernet/DMA"
To quote the author:
Since commit [1], Ethernet is broken on TI AM62 and AM64 platforms.
The commit [1] is not the culprit. It just unearths the problem by fixing
the error check in k3-udma.c. This issue was silently being ignored earlier
due to wrong error check. [NULL instead of FDT_ADDR_T_NONE].
Fix the issue by adding the necessary register spaces for the u-boot K3-UDMA
driver for AM62 and AM64 platforms.
These properties will eventually make it into the SoC DTSi files [2] after
which these can be dropped from k3-*-u-boot.dtsi files.
[1] - 5fecea171de3dd ("treewide: use dev_read_addr_*_ptr() where appropriate")
[2] - https://lore.kernel.org/linux-arm-kernel/20230810174356.3322583-1-vigneshr@ti.com/
Update main_bcdma and main_pktdma nodes for native configuration in the
absence of DM services. u-boot k3-udma driver expects these additional
register fields else probe will fail.
Tom Rini [Fri, 10 Nov 2023 16:55:28 +0000 (11:55 -0500)]
Merge branch '2023-11-10-improve-semihosting-armv6' into next
To quote the author:
This series has a few fixes for semihosting on ARMv6 and older CPUs. The
first two patches address problems regarding the stack pointer and link
register. U-Boot runs in supervisor mode, so taking a software interrupt
will clobber sp/lr. I think we really should run in system mode, since
it has separate sp/lr registers. To quote ARM DDI 0100I:
> The remaining mode is System mode, which is not entered by any
> exception and has exactly the same registers available as User mode.
> However, it is a privileged mode and is therefore not subject to the
> User mode restrictions. It is intended for use by operating system
> tasks that need access to system resources, but wish to avoid using
> the additional registers associated with the exception modes. Avoiding
> such use ensures that the task state is not corrupted by the
> occurrence of any exception.
However, the processor mode has been supervisor for such a long time
(since relocation got introduced) that I would rather not touch it.
Sean Anderson [Fri, 27 Oct 2023 20:40:15 +0000 (16:40 -0400)]
arm: semihosting: Support semihosting fallback on 32-bit ARM
Add support for a semihosting fallback on 32-bit ARM. The assembly is
lightly adapted from the irq return code, except there is no offset
since lr already points to the correct instruction. The C side is mostly
like ARM64, except we have fewer cases to deal with.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Fri, 27 Oct 2023 20:40:14 +0000 (16:40 -0400)]
arm: semihosting: Fix returning from traps on ARMv6 and lower
U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts
are taken in supervisor mode. When entering an interrupt, the link
register is set to the address of the next instruction. However, if we
are already in supervisor mode, this clobbers the link register. The
debugger can't help us, since by the time it notices we've taken a
software interrupt, the link register is already gone. Work around this
by moving the return address to another register.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Fri, 27 Oct 2023 20:40:13 +0000 (16:40 -0400)]
arm: Fix software interrupt handler
When we take a software interrupt, we are already in supervisor mode.
get_bad_stack assumes we are not in supervisor mode so it can clobber
the stack pointer. This causes us to have an invalid stack once that
macro finishes. Revert back to the get_bad_stack_swi macro which was
previously removed.
Fixes: 41623c91b09 ("arm: move exception handling out of start.S files") Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Tom Rini [Fri, 10 Nov 2023 14:43:01 +0000 (09:43 -0500)]
Merge tag 'u-boot-stm32-20231110' of https://source.denx.de/u-boot/custodians/u-boot-stm
_ Fix compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled
_ Fix issue following DT sync with kernel 6.3 for stm32mp15xx-ev1 and DHSOM SoM
_ Enable TCP, IPv6, wget on DH STM32MP15 DHSOM
_ Limit u-boot.itb size to 0x160000 bytes on DH STM32MP15 DHSOM
_ Read auth stats and boot_partition from tamp
Tom Rini [Fri, 10 Nov 2023 13:44:18 +0000 (08:44 -0500)]
Merge branch '2023-11-10-assorted-fixes'
- Fix some issues Coverity has reported, update MAINTAINERS file,
another bootstd fix, typo fix in error message, gitignore fix and
update TI's URL in many places.
Sam Protsenko [Thu, 26 Oct 2023 21:00:15 +0000 (16:00 -0500)]
tools: gitignore: Fix tools/generated path
'git status' shows 'tools/generated/' after running the build, which is
wrong. The corresponding .gitignore rule was already added in commit c623642d29be ("Adjust gitignore for tools/generated/"), but because of
superfluous 'tools/' part it wasn't in effect. Remove incorrect 'tools/'
part to fix it.
While at it, remove tools/ path incorrectly added to the top-level
.gitignore in commit 801c482207c7 (".gitignore: ignore misc include,
simple-bin, and tools/generated build artifacts"), as it's required in
the comment on the top of .gitignore:
# NOTE! Don't add files that are generated in specific
# subdirectories here. Add them in the ".gitignore" file
# in that subdirectory instead.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Fixes: c623642d29be ("Adjust gitignore for tools/generated/") Fixes: 801c482207c7 (".gitignore: ignore misc include, simple-bin, and tools/generated build artifacts")
Tony Dinh [Thu, 2 Nov 2023 18:51:15 +0000 (11:51 -0700)]
bootstd: Skip over bad device during bootflows scanning
During bootstd scanning for bootdevs, if bootdev_hunt_drv() encounters
a device not found error (e.g. ENOENT), let it return a successful status
so that bootstd will continue scanning the next devices, not stopping
prematurely.
Background:
During scanning for bootflows, it's possible for bootstd to encounter a
faulty device controller. Also when the same u-boot is used for another
variant of the same board, some device controller such as SATA might
not exist.
I've found this issue while converting the Marvell Sheevaplug board to
use bootstd. This board has 2 variants, the original Sheevaplug has MMC and
USB only, but the later variant comes with USB, MMC, and eSATA ports. We
have been using the same u-boot (starting with CONFIG_IDE and later with DM
CONFIG_SATA) for both variants. This worked well with the old
envs-scripting booting scheme.
Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 8 Nov 2023 19:28:11 +0000 (14:28 -0500)]
scsi: Have scsi_init_dev_desc_priv() use memset
When we do not have CONFIG_BOUNCE_BUFFER enabled, inside of
scsi_init_dev_desc_priv we never set the 'bb' field to false, we only
initialize it to true when CONFIG_BOUNCE_BUFFER is set. Given that we
have a number of other fields here we had been explicitly setting to
zero, change to first calling memset to clear the struct and then
initialize only the fields that need non-zero default values.
Addresses-Coverity-ID: 467407 ("Uninitialized variables (UNINIT)") Fixes: 81bd22e935dc ("rockchip: block: blk-uclass: add bounce buffer flag to blk_desc") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Keep track of the re-entries with help of the lr register.
This binary can be re-used and called from various BROM functions.
Only when it's called from the part that handles SPI, NAND or EMMC
hardware it needs to early return to BROM ones.
In download mode when it handles data on USB OTG and UART0
this section must be skipped.
Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
support to enter download mode on return to BROM. This binary must check
the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
It then returns to BROM to the end of the function that reads boot blocks.
From there the BROM code goes into a download mode and waits for data
on USB OTG and UART0.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Fri, 3 Nov 2023 09:28:13 +0000 (10:28 +0100)]
rockchip: ringneck-px30: enable SPL_BOARD_INIT
Now that Ringneck requires some board-specific code (namely resetting
the MCU companion controller) to be run during SPL stage, let's enable
SPL_BOARD_INIT.
Quentin Schulz [Fri, 3 Nov 2023 09:28:12 +0000 (10:28 +0100)]
rockchip: ringneck-px30: always reset STM32 companion controller on boot
It's happened that glitches on the STM32_RST and STM32_BOOT lines have
put the STM32 companion microcontroller into DFU mode making it not boot
its FW, rendering it useless for the user.
Considering that the STM32 companion microcontroller is always reset on
a reboot or power cycle, resetting it once again in U-Boot SPL isn't
going to hurt it any more.
For ATtiny companion microcontroller, the situation is a bit different
because a reboot or power cycle doesn't reset it. Additionally, since it
can only be reset with a UPDI reset on the STM32_RST line, and that is
virtually impossible to mistakenly trigger, the ATtiny is unlikely to be
in unwanted reset or enter reset because U-Boot toggles STM32_RST line.
Tim Lunn [Mon, 30 Oct 2023 13:12:41 +0000 (00:12 +1100)]
rockchip: dts: fix bootph tags for rv1126
RV1126 fails to boot on 2024.01-rc1.
Commit 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as
pre-reloc after relocation") changed the behaviour of bootph-pre-ram, to
limit nodes to spl phase. This caused rv1126 boards to fail to boot with
the current dts.
This patch updates the pmu/grf nodes to bootph-all tags as they are
needed in all phases. This fixes the boot issue on rv1126 boards.
Signed-off-by: Tim Lunn <tim@feathertop.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Igor Opaniuk [Mon, 6 Nov 2023 10:41:52 +0000 (11:41 +0100)]
stm32mp1: read auth stats and boot_partition from tamp
Obtain from TAMP backup register information about image authorization
status and partition id used for booting. Store this info in
environmental variables ("boot_auth" and "boot_part" correspondingly).
Image authorization supported values:
0x0 - No authentication done
0x1 - Authentication done and failed
0x2 - Authentication done and succeeded
These values are stored to TAMP backup register by Trusted Firmware-A [1].
Marek Vasut [Sat, 4 Nov 2023 16:31:57 +0000 (17:31 +0100)]
arm: stm32: Limit u-boot.itb size to 0x160000 bytes on DH STM32MP15 DHSOM
The maximum size of u-boot.itb in SPI NOR on DH STM32MP15 DHSOM is
0x160000 . Define this size in U-Boot config to prevent misconfigured
builds from emitting larger u-boot.itb than the one which fits the
SPI NOR area reserved for the blob.
The SPI NOR layout is as follows:
0x00_0000..0x03_ffff ... SPL 1
0x04_0000..0x07_ffff ... SPL 2
0x08_0000..0x1d_ffff ... U-Boot
0x1e_0000..0x1e_ffff ... Environment 1
0x1f_0000..0x1f_ffff ... Environment 2
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Sat, 4 Nov 2023 16:31:56 +0000 (17:31 +0100)]
arm: stm32: Enable TCP, IPv6, wget on DH STM32MP15 DHSOM
Enable support for TCP protocol, wget, and IPv6 on this platform.
The former two allow users download payload into the U-Boot from
a web server, which may be more convenient or easier to set up
than TFTP server. The later is enabled to future proof the IP
stack on this platform.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Mon, 9 Oct 2023 23:15:51 +0000 (01:15 +0200)]
ARM: dts: stm32mp: Repair damage from alignment with v6.3
The patch fixed by this commit renders ST STM32MP15xx EV1 board and
all DHSOM SoM based boards unbootable from SPI NOR. Fix the damage
by updating -u-boot.dtsi to match the stm32mp15-pinctrl.dtsi update.
Fixes: 08002ffd083d ("ARM: dts: stm32mp: alignment with v6.3") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Bhupesh Sharma [Tue, 22 Aug 2023 07:51:11 +0000 (13:21 +0530)]
arm: stm32mp: Really fix compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled
While 23e20b2fa6 ("arm: stm32mp: Fix compilation issue when
SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled") tried fixing
this issue, fix it really by adding #if checks for SYS_ICACHE_OFF
and SYS_DCACHE_OFF.
Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
projects / thirdparty / u-boot.git / log
