Andrew Goodbody [Mon, 1 Sep 2025 15:13:14 +0000 (16:13 +0100)]
spi: exynos: Remove extra term from test
In spi_rx_tx there comes a test for execution of a code block that
allows execution if rxp is not NULL or stopping is true. However all the
code in this block relies on rxp being valid so allowing entry just if
stopping is true does not make sense. So remove this from the test
expression leaving just a NULL check for rxp.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Andrew Goodbody [Thu, 7 Aug 2025 14:41:18 +0000 (15:41 +0100)]
pinctrl: rzg2l: Variable may not have been assigned to
In rzg2l_pinconf_set and rzg2l_get_pin_muxing if the call to
rzg2l_selector_decode fails then the variable pin may not have been
assigned to. Remove the use of pin from the error message. Also update
the error message to show the invalid selector used instead of port
which will be the error code returned.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Paul Barker <paul@pbarker.dev> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tom Rini [Tue, 2 Sep 2025 20:11:45 +0000 (14:11 -0600)]
Merge patch series "memtest performance improvements"
Rasmus Villemoes <ravi@prevas.dk> says:
The first two patches make memtest run ~40x faster (when, as it should
be, dcache is disabled), with the second patch being responsible for
most of that. At least on the beagleboneblack which I used for
testing; other boards and configurations will likely see different
numbers.
This is for CONFIG_SYS_ALT_MEMTEST=y and
CONFIG_SYS_ALT_MEMTEST_BITFLIP=n; one could probably get a similar
improvement in the bitflip case since that also has a schedule() call
in the inner loop.
Rasmus Villemoes [Fri, 22 Aug 2025 18:18:48 +0000 (20:18 +0200)]
memtest: remove use of vu_long typedef in mem_test_alt
Hiding a qualifier such as "volatile" inside a typedef makes the code
much harder to understand. Since addr and dummy being
volatile-qualified are important for the correctness of the test code,
make it more obvious by spelling it out as "volatile ulong".
Rasmus Villemoes [Fri, 22 Aug 2025 18:18:47 +0000 (20:18 +0200)]
memtest: only call schedule() once for every 256 words
A function call itself for every word written or read+written in these
loops is bad enough. But since the memory test must be run with dcache
disabled, the schedule() call, traversing the linked list of
registered cyclic clients, and accessing the 'struct cyclic_info' for
each to see if any are due for a callback, is quite expensive. On a
beagleboneblack, testing a modest 16MiB region takes 2.5 minutes:
=> dcache off
=> time mtest 0x81000000 0x82000000 0 1
Testing 81000000 ... 82000000:
Iteration: 1
Tested 1 iteration(s) with 0 errors.
time: 2 minutes, 28.946 seconds
There is really no need for calling schedule() so frequently. It is
quite easy to limit the calls to once for every 256 words by using a
u8 variable. With that, the same test as above becomes 37 times
faster:
=> dcache off
=> time mtest 0x81000000 0x82000000 0 1
Testing 81000000 ... 82000000:
Iteration: 1
Tested 1 iteration(s) with 0 errors.
during those ~4000 milliseconds, so the schedule() calls are still
done less than 0.1ms apart.
These numbers are just for a beagleboneblack, other boards may have a
slower memory, but we are _two orders of magnitude_ away from
schedule() "only" being called at 100Hz, which is still more than
enough to ensure any watchdog is kept happy.
Rasmus Villemoes [Fri, 22 Aug 2025 18:18:46 +0000 (20:18 +0200)]
memtest: don't volatile-qualify local variables
It is obviously important that the addr pointer used to access the
memory region being tested is volatile-qualified, to prevent the
compiler from optimizing out the "write this value, read it back,
check that it is what we expect".
However, none of these auxiliary variables have any such need for,
effectively, being forced to live on the stack and cause each and
every reference to them to do a memory access.
This makes the memtest about 15% faster on a beagleboneblack.
Before:
=> dcache off
=> time mtest 0x81000000 0x81100000 0 1
Testing 81000000 ... 81100000:
Iteration: 1
Tested 1 iteration(s) with 0 errors.
time: 10.868 seconds
After:
=> dcache off
=> time mtest 0x81000000 0x81100000 0 1
Testing 81000000 ... 81100000:
Iteration: 1
Tested 1 iteration(s) with 0 errors.
time: 9.209 seconds
[Without the 'dcache off', there's no difference in the time, about
0.6s, but the memtest cannot usefully be done with dcache enabled.]
- Update compatibles for PMICs used by exynos devices
- Support system reset and reset status for pca9450
- Fix for pca9450 LDO5 registers and drop deprecated sd-vsel-gpios
- Two minor fixes found by smatch
Henrik Grimler [Fri, 22 Aug 2025 18:54:38 +0000 (20:54 +0200)]
ARM: exynos: use correct exynos4210-origen SoC in Kconfig
There exists both a Origen board based on exynos4210, and a board
based on exynos4412. U-boot only supports the one based on exynos
4210, but Kconfig string was accidentally written as Exynos4412 Origen
in previous migration to Kconfig. Fix the string to clear up
confusion, and to not give the impression that both types of Origen
boards are supported.
Fixes: 72df68cc6b73 ("exynos: kconfig: move board select menu and common settings") Signed-off-by: Henrik Grimler <henrik@grimler.se> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
ARM: tegra20: transformer: fix Hall sensor behavior
Hall sensor found in SL101 is not used for closed dock detection as on
TF101 or TF101G, it is used to detect if keyboard slider is out. To address
this, lets move Lid sensor switch into TF101/G trees and add Tablet mode
switch into SL101 tree.
Sam Protsenko [Wed, 6 Aug 2025 22:27:10 +0000 (17:27 -0500)]
configs: e850-96: Enable Ethernet
LAN9514 is a chip on E850-96 board which acts as a USB host hub and
Ethernet controller. It's controlled via USB lines when DWC3 is
configured to be in USB host role (by setting the "dr_mode" property to
"host" value in e850-96 dts file).
Enable network support and LAN9514 chip support. This makes Ethernet
functional on E850-96 board.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:09 +0000 (17:27 -0500)]
configs: e850-96: Enable USB host support
Exynos850 SoC has a dual-role USB controller which can be configured in
USB host role. As it's the only one USB controller on the board, it's
shared between "device" USB connector (micro-USB) and host USB
connectors. The hardware automatically powers on the host related parts
when the micro-USB cable (for device role) is being disconnected. Also,
as U-Boot lacks dynamic USB role switching capability, the only way to
switch the role at the moment is to modify "dr_mode" property in
U-Boot's device tree file here:
Sam Protsenko [Wed, 6 Aug 2025 22:27:08 +0000 (17:27 -0500)]
configs: e850-96: Disable CONFIG_DEFAULT_FDT_FILE
Linux kernel should use some separate device tree obtained from another
source anyway. For example the dtb file can be read from /boot directory
in eMMC rootfs partition, either by GRUB or U-Boot. Using U-Boot's
device tree blob to provide it to the kernel (when
CONFIG_DEFAULT_FDT_FILE is set and nobody else overrides this choice)
might lead to undesired effects when booting the OS. For example, if a
user sets "dr_mode" property to "host" value in U-Boot's dts to enable
USB host capabilities in U-Boot, it might confuse usb-conn-gpio driver
in Linux kernel later like this:
platform connector: deferred probe pending: usb-conn-gpio:
failed to get role switch
Disable CONFIG_DEFAULT_FDT_FILE option to avoid any possible confusion.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:07 +0000 (17:27 -0500)]
board: samsung: e850-96: Add bootdev var to choose boot device
Provide a way for the user to select which storage to load the LDFW
firmware from, by setting the corresponding environment variables:
- bootdev: block device interface name
- bootdevnum: block device number
- bootdevpart: partition number
This might be useful when the OS is flashed and booted from a different
storage device than eMMC (e.g. USB flash drive). In this case it should
be sufficient to just set:
=> setenv bootdev usb
=> env save
assuming that the USB drive layout follows the same partitioning scheme
as defined in $partitions.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:06 +0000 (17:27 -0500)]
board: samsung: e850-96: Extract device info from fw loading code
Make it possible to provide the information about storage device where
LDFW firmware resides to the firmware loading routine. The firmware
loader code shouldn't have that data hard-coded anyway, and it also
allows for implementing more dynamic behavior later, like choosing the
storage device containing LDFW via some environment variables.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Make use of PMIC configuration routines and enable all LDOs that might
be useful for bootloader and kernel. The most crucial regulator being
enabled at the moment is LDO24 which provides power to LAN9514 chip.
That makes Ethernet controller and USB hub functional.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:04 +0000 (17:27 -0500)]
board: samsung: e850-96: Add PMIC code
Add functions for configuring voltage regulators on S2MPU12 PMIC chip
for E850-96 board. The chip is accessed by commanding APM core (via
ACPM IPC protocol) to perform corresponding transfers over I3C bus.
The most important regulator being set up is LDO24 used for LAN9514 chip
power. As LAN9514 implements USB hub and Ethernet controller
functionality, it's crucial to enable and configure LDO24 to be able to
use it further. While at it, configure the rest of regulators that might
be needed later, both in the bootloader and in kernel.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:03 +0000 (17:27 -0500)]
board: samsung: e850-96: Add ACPM code
Add functions to access I3C bus via APM (Active Power Management) core
by using ACPM IPC protocol. It will be further used for configuring PMIC
chip voltage regulators.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:02 +0000 (17:27 -0500)]
board: samsung: e850-96: Set ethaddr
Set the environment variable for Ethernet MAC address (ethaddr). Use the
SoC ID to make sure it's unique. It'll be formatted in a way that
follows the consecutive style of the serial number ("serial#" variable),
i.e.:
Enable support for Exynos850 SoC in DWC3 host glue layer driver.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Andrew Goodbody [Wed, 23 Jul 2025 16:04:41 +0000 (17:04 +0100)]
clk: exynos: Fix always true test
In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Andrew Goodbody [Wed, 30 Jul 2025 16:52:56 +0000 (17:52 +0100)]
mmc: iproc_sdhci: Cannot test unsigned variable for negative
In sdhci_iproc_execute_tuning the variable tuning_loop_counter is
unsigned and therefore will always fail the test for it being less than
0. Fix this by changing the variable type to be s8.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Primoz Fiser [Thu, 28 Aug 2025 11:24:05 +0000 (13:24 +0200)]
power: pmic: pca9450: Add support for reset status
PCA9450 PMIC supports reading the reset status from the PWRON_STAT
register. Bits 7-4 give indication of the PMIC reset cause:
- PWRON (BIT7) - Power ON triggered by PMIC_ON_REQ input line,
- WDOGB (BIT6) - Boot after cold reset by WDOGB pin (watchdog reset),
- SW_RST (BIT5) - Boot after cold reset initiated by the software,
- PMIC_RST (BIT4) - Boot after PMIC_RST_B input line trigger.
Add support for reading reset status via the sysreset framework in a
convenient printable format.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Paul Geurts <paul.geurts@prodrive-technologies.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Primoz Fiser [Thu, 28 Aug 2025 11:24:04 +0000 (13:24 +0200)]
power: pmic: pca9450: Add support for system reset
The family of PCA9450 PMICs have the ability to perform system resets.
Restarting via PMIC is preferred method of restarting the system as all
the peripherals are brought to a know state after a power-cycle. The
PCA9450 features a cold restart procedure which is initiated by an I2C
command 0x14 to the SW_RST register.
Support in Linux for restarting via PCA9450 PMIC has been added by
Linux commit 6157e62b07d9 ("regulator: pca9450: Add restart handler").
Now add support for it also in the U-Boot via sysreset framework.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Paul Geurts <paul.geurts@prodrive-technologies.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Henrik Grimler [Fri, 22 Aug 2025 18:33:33 +0000 (20:33 +0200)]
board: samsung: odroid: drop exynos_power_init
exynos_power_init sets up regulators for the emmc and sdcard, but
these regulators are already marked as always-on and boot-on and hence
are handled already by the regulator-uclass. Since we currently try to
set them up twice we get error -114 (EALREADY) from exynos_power_init
on every boot:
LDO20@VDDQ_EMMC_1.8V: set 1800000 uV; enabling (ret: -114)
LDO22@VDDQ_EMMC_2.8V: set 2800000 uV; enabling (ret: -114)
LDO21@TFLASH_2.8V: set 2800000 uV; enabling (ret: -114)
Remove the superfluous exynos_power_init to silence these errors.
Signed-off-by: Henrik Grimler <henrik@grimler.se> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Henrik Grimler [Fri, 22 Aug 2025 18:33:23 +0000 (20:33 +0200)]
power: pmic: s2mps11: look for both {voltage-,}regulators
Linux's DTSes uses regulators { }; while u-boot's DTSes uses
voltage-regulators { };. Look for regulators, and fallback to
voltage-regulators if not found, so that both type of DTSes can be
used with the driver.
Signed-off-by: Henrik Grimler <henrik@grimler.se> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
The sd-vsel-gpios property in the root of the PMIC node is deprecated
and therefore not parsed by the driver anymore. We can safely remove
this as it wasn't used anyway due to the pad not having the correct
pinmux settings.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
The sd-vsel-gpios property in the root of the PMIC node is deprecated
and therefore not parsed by the driver anymore. We can safely remove
this as it wasn't used anyway due to the pad not having the correct
pinmux settings.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Frieder Schrempf [Mon, 11 Aug 2025 13:12:00 +0000 (15:12 +0200)]
pmic: pca9450: Handle hardware with fixed SD_VSEL for LDO5
There are two ways to set the output voltage of the LD05
regulator. First by writing to the voltage selection registers
and second by toggling the SD_VSEL signal.
Usually board designers connect SD_VSEL to the VSELECT signal
controlled by the USDHC controller, but in some cases the
signal is hardwired to a fixed low level (therefore selecting
3.3V as initial value for allowing to boot from the SD card).
In these cases, the voltage is only determined by the value
of the LDO5CTRL_L register. Introduce a property
nxp,sd-vsel-fixed-low to let the driver know that SD_VSEL
is low and there is no GPIO to actually get that
information from dynamically.
This is equivalent to the following change in Linux:
c8c1ab2c5cb7 ("regulator: pca9450: Handle hardware with fixed SD_VSEL for LDO5")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Frieder Schrempf [Mon, 11 Aug 2025 13:11:59 +0000 (15:11 +0200)]
pmic: pca9450: Fix control register for LDO5
For LDO5 we need to be able to check the status of the SD_VSEL input in
order to know which control register is used. Read the status of the
SD_VSEL signal via GPIO and use the correct register accordingly.
To use this, the LDO5 node in the devicetree needs the sd-vsel-gpios
property to reference the GPIO that is used to read back the SD_VSEL
status internally. Please note that the SION bit in the IOMUX must be
set if the signal is muxed as VSELECT and controlled by the USDHC
controller.
This is equivalent to the following change in Linux:
3ce6f4f943dd ("regulator: pca9450: Fix control register for LDO5")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
It turns out that all boards using the PCA9450 actually have the
SD_VSEL input connected to the VSELECT signal of the SoCs SD/MMC
interface. Therefore we don't need manual control for this signal
via GPIO and there aren't any users.
This is equivalent to the following change in Linux:
c73be62caabb ("Revert "regulator: pca9450: Add SD_VSEL GPIO for LDO5"")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Thu, 7 Aug 2025 16:35:22 +0000 (17:35 +0100)]
power: regulator: tps65910: Cannot test unsigned for being negative
The code in tps65910_regulator.c treats the field supply in struct
tps65910_regulator_pdata as an int and even tests the value for being
negative so change it from a u32 to int so that the code all works as
expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Fri, 29 Aug 2025 22:45:27 +0000 (16:45 -0600)]
Merge patch series "power: regulator: Fix some Smatch reported issues"
Andrew Goodbody <andrew.goodbody@linaro.org> says:
Smatch reported some issues in the regulator drivers, mostly repeated
instances of testing an unsigned variable for being negative but also an
expression needing parenthesis to be interpreted as expected.
[trini: Drop 5/6 for now due to changes being requested on review]
Tom Rini [Fri, 4 Jul 2025 21:50:21 +0000 (15:50 -0600)]
power: Split *POWER_LEGACY portion of <power/pmic.h> out to new header
The commends in include/power/pmic.h say that once SPL_DM_PMIC exists we
should update things. This has been true for some time, so let us update
this to have the legacy portions in their own header, which should not
be directly included. This cleans up the logic within the file too
slightly.
Adriano Carvalho [Mon, 25 Aug 2025 22:32:28 +0000 (23:32 +0100)]
doc: Fix obvious typos and minor improvements
These are fixes to what looks like obvious typos.
Some minor improvments are also included, such as:
- Write "symbolic link" instead of symlink
- Correct capitalization for LLVM (all caps)
- Remove dead link and surrounding sentence
Tom Rini [Tue, 12 Aug 2025 18:01:32 +0000 (12:01 -0600)]
efi_loader: Make EFI_VARIABLES_PRESEED depend on !COMPILE_TEST
When doing compile testing build we cannot rely on having a valid file
for EFI_VAR_SEED_FILE to exist, so disable this option when doing
compile tests.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Andrew Goodbody [Mon, 11 Aug 2025 12:05:15 +0000 (13:05 +0100)]
efi: serial: Use correct EFI status type
int is not sufficient to hold and test the return from an EFI function
call. Use efi_status_t instead so that the test can work as expected.
This issue was found by Smatch.
Fixes: 275854baeeec ("efi: Add a serial driver") Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:19 +0000 (22:07 +0000)]
rockchip: rk3588-generic: Move usb nodes to board dts
After the commit 7a53abb18325 ("rockchip: rk3588: Remove USB3 DRD nodes
in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the
usb nodes for the Generic RK3588 board in the board u-boot.dtsi.
Move usb related nodes from board u-boot.dtsi to main board device tree.
While at it, also drop use of the usb3-phy as we only want to enable the
usb2-phy to be compatible with as many boards as possible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:18 +0000 (22:07 +0000)]
rockchip: rk3576: Disable USB3OTG0 U3 port early
The RK3576 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).
Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG0 U3 port early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:17 +0000 (22:07 +0000)]
rockchip: rk3588: Disable USB3OTG U3 ports early
The RK3588 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).
Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 ports early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:13 +0000 (22:07 +0000)]
phy: rockchip: naneng-combphy: Simplify init ops
The init ops for Rockchip COMBPHY driver is more complex than it needs
to be, e.g. declaring multiple init functions that only differ in the
error message.
Simplify the init ops based on code from the Linux mainline driver.
This change also ensure that errors returned from combphy_cfg() and
reset_deassert_bulk() is propertly propagated to the caller. No other
runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip COMBPHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:11 +0000 (22:07 +0000)]
phy: rockchip: usbdp: Simplify init ops
With working shared reference counting for Generic PHY ops there is no
need for the Rockchip USBDP PHY driver to keep its own status (reference
counting) handling.
Simplify the init ops now that shared reference counting is working.
This also removes the unused mode_change handling as part of the
simplication.
No runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
E.g. on a ROCK 5B following could be observed:
=> usb start
starting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb reset
resetting USB...
[...]
rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
rockchip_udphy phy@fed90000: failed to init usbdp combophy
rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
Can't init PHY1
Bus usb@fc400000: probe failed, error -110
scanning usb for storage devices... 0 Storage Device(s) found
With shared reference counting this is fixed:
=> usb reset
resetting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andrew Goodbody [Thu, 31 Jul 2025 11:46:10 +0000 (12:46 +0100)]
mmc: rockchip_sdhci: Do not test unsigned for being less than 0
In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is
tested for being less than 0. Ensure that it is a signed type by
declaring it as s8 instead of char.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 13 Aug 2025 14:07:43 +0000 (16:07 +0200)]
power: rk8xx: allow to customize RK806 reset mode
The RK806 PMIC has a bitfield for configuring the restart/reset behavior
(which I assume Rockchip calls "function") whenever the PMIC is reset
either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL
or RESETB pins.
For RK806, the following values are possible for RST_FUN:
0b00 means "Restart PMU"
0b01 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode"
0b10 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode, and simultaneously
pull down the RESETB PIN for 5mS before releasing"
0b11 means the same as for 0b10 just above.
This adds the appropriate logic in the driver to parse the new
rockchip,reset-mode DT property to pass this information. It just
happens that the values in the binding match the values to write in the
bitfield so no mapping is necessary.
For backward compatibility reasons, if the property is missing we set it
to 0b10 (i.e. BIT(7)) like before this commit was merged instead of
leaving it untouched like in the kernel driver.
Note that this does nothing useful for U-Boot at the moment as the ways
to reset the device (e.g. via `reset` command) doesn't interact with the
RK8xx PMIC and simply does a CPU reset.
Considering the upstream Linux kernel left this register untouched until
(assumed) v6.17[1], this is useful for cases in which the U-Boot
bootloader has this patch (and running with a DT with
rockchip,reset-mode property set) and running an upstream kernel before
(assumed) v6.17, or alternatively later without the property in the
kernel DT.
Quentin Schulz [Wed, 13 Aug 2025 14:07:42 +0000 (16:07 +0200)]
arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger
The bootloader for RK3588 Tiger currently forces the PMIC reset behavior
(stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X
which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Quentin Schulz [Wed, 13 Aug 2025 14:07:41 +0000 (16:07 +0200)]
arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar
The bootloader for RK3588 Jaguar currently forces the PMIC reset
behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC)
to 0b1X which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Quentin Schulz [Wed, 13 Aug 2025 14:07:40 +0000 (16:07 +0200)]
arm64: dts: rockchip: add header for RK8XX PMIC constants
To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.
Quentin Schulz [Wed, 13 Aug 2025 14:07:39 +0000 (16:07 +0200)]
dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
The RK806 PMIC allows to configure its reset/restart behavior whenever
the PMIC is reset either programmatically or via some external pins
(e.g. PWRCTRL or RESETB).
The following modes exist:
- 0; restart PMU,
- 1; reset all power off reset registers and force state to switch to
ACTIVE mode,
- 2; same as mode 1 and also pull RESETB pin down for 5ms,
For example, some hardware may require a full restart (mode 0) in order
to function properly as regulators are shortly interrupted in this mode.
This is the case for RK3588 Jaguar and RK3588 Tiger which have a
companion microcontroller running on an independent power supply and
monitoring the PMIC power rail to know the state of the main system.
When it detects a restart, it resets its own IPs exposed to the main
system as if to simulate its own reset. Failing to perform this fake
reset of the microcontroller may break things (e.g. watchdog not
automatically disabled, buzzer still running until manually disabled,
leftover configuration from previous main system state, etc...).
Some other systems may be depending on the power rails to not be
interrupted even for a small amount of time[1].
This allows to specify how the PMIC should perform on the hardware level
and may differ between hardware designs, so a DT property seems
warranted. I unfortunately do not see how this could be made generic
enough to make it a non-vendor property.
Jonas Karlman [Wed, 30 Jul 2025 23:52:45 +0000 (23:52 +0000)]
rockchip: rk3528: Disable USB3OTG U3 port early
The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).
Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
projects / thirdparty / u-boot.git / log
