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(parent: 2293b0a) | patch
x86: Only align destination to 1x VEC_SIZE in memset 4x loop
authorNoah Goldstein <goldstein.w.n@gmail.com>
Wed, 1 Nov 2023 20:30:26 +0000 (15:30 -0500)
committerSunil K Pandey <skpgkp2@gmail.com>
Sat, 11 Jan 2025 23:29:30 +0000 (15:29 -0800)
commit4d4dcf98ac122733d1d63e638b3d5560720cee7d
tree82467c1e53582cf387235050e201624bde0f1901tree
parent2293b0a0d044fe1e64a9579752ce6e7176718064commit | diff
x86: Only align destination to 1x VEC_SIZE in memset 4x loop

Current code aligns to 2x VEC_SIZE. Aligning to 2x has no affect on
performance other than potentially resulting in an additional
iteration of the loop.
1x maintains aligned stores (the only reason to align in this case)
and doesn't incur any unnecessary loop iterations.
Reviewed-by: Sunil K Pandey <skpgkp2@gmail.com>
(cherry picked from commit 9469261cf1924d350feeec64d2c80cafbbdcdd4d)
sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S diff | blob | blame | history
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