]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commit
[AArch64][SVE 29/32] Add new SVE core & FP register operands
authorRichard Sandiford <richard.sandiford@arm.com>
Fri, 17 Jun 2016 13:55:00 +0000 (14:55 +0100)
committerRichard Sandiford <richard.sandiford@arm.com>
Tue, 23 Aug 2016 08:41:04 +0000 (09:41 +0100)
commit936b52907bc22f1f0c4c4bf7865d6f70ceb25eb2
tree188c203a200671a5fa4ae0ed1a8e485453057e35
parentaf2b6e952f8f96fd4cd02fc8dac03ed354695eca
[AArch64][SVE 29/32] Add new SVE core & FP register operands

SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.

include/opcode/
* aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
and FP register operands.
* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
(FLD_SVE_Vn): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(aarch64_print_operand): Handle the new SVE core and FP register
operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm-2.c: Likewise.
* aarch64-dis-2.c: Likewise.

gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE core
and FP register operands.

Change-Id: Icb683553ba080e25c1de2449fa6e9030e48eba36
gas/config/tc-aarch64.c
include/opcode/aarch64.h
opcodes/aarch64-asm-2.c
opcodes/aarch64-dis-2.c
opcodes/aarch64-opc-2.c
opcodes/aarch64-opc.c
opcodes/aarch64-opc.h
opcodes/aarch64-tbl.h