RISC-V: Allow LICM hoist POLY_INT configuration code sequence

RISC-V: Allow LICM hoist POLY_INT configuration code sequence

Realize in recent benchmark evaluation (coremark-pro zip-test):

        vid.v   v2
        vmv.v.i v5,0
.L9:
        vle16.v v3,0(a4)
        vrsub.vx        v4,v2,a6   ---> LICM failed to hoist it outside the loop.

The root cause is:

(insn 56 47 57 4 (set (subreg:DI (reg:HI 220) 0)
        (reg:DI 223)) "rvv.c":11:9 208 {*movdi_64bit}  -> Its result used by the following vrsub.vx then supress the hoist of the vrsub.vx
     (nil))

(insn 57 56 59 4 (set (reg:RVVMF2HI 216)
        (if_then_else:RVVMF2HI (unspec:RVVMF32BI [
                    (const_vector:RVVMF32BI repeat [
                            (const_int 1 [0x1])
                        ])
                    (reg:DI 350)
                    (const_int 2 [0x2]) repeated x2
                    (const_int 1 [0x1])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (minus:RVVMF2HI (vec_duplicate:RVVMF2HI (reg:HI 220))
                (reg:RVVMF2HI 217))
            (unspec:RVVMF2HI [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF))) "rvv.c":11:9 6938 {pred_subrvvmf2hi_reverse_scalar}
     (expr_list:REG_DEAD (reg:HI 220)
        (nil)))

This patch fixes it generate (set (reg:HI) (subreg:HI (reg:DI))) instead of (set (subreg:DI (reg:DI)) (reg:DI)).

After this patch:

	vid.v	v2
	vrsub.vx	v2,v2,a7
	vmv.v.i	v4,0
.L3:
	vle16.v	v3,0(a4)

Tested on both RV32 and RV64 no regression.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/poly_licm-1.c: New test.
	* gcc.target/riscv/rvv/autovec/poly_licm-2.c: New test.
	* gcc.target/riscv/rvv/autovec/poly_licm-3.c: New test.