[Morello] Load and branch instructions

[Morello] Load and branch instructions

- BR, BLR
- LDPBR, LDPBLR

This branch instructions take an address as their target operand.  The
important distinction between the address register usage between these
instructions and other load and store instructions is that these
instructions do not support 64-bit registers as addresses.

gas/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* config/tc-aarch64.c (aarch64_addr_reg_parse): Add capability
	registers.
	(parse_address_main): Support capability address operands.
	(parse_cap_address): New function.
	(parse_operands): Add CAPADDR_SIMPLE and CAPADDR_SIMM7.
	* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
	* testsuite/gas/aarch64/morello_ldst.d: Likewise.
	* testsuite/gas/aarch64/morello_ldst.s: Likewise.

include/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add CAPADDR_SIMPLE and
	CAPADDR_SIMM7.
	(aarch64_insn_class): Add br_capaddr.

opcodes/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* aarch64-asm.c (aarch64_ins_addr_simple): Fix comment.
	(aarch64_ins_addr_simm): Support capability address operands.
	* aarch64-dis.c (aarch64_ext_addr_simple): Fix comment.
	(aarch64_ext_addr_simm): Support capability address operands.
	* aarch64-opc.c (fields): Add capaddr_simm7.
	(operand_general_constraint_met_p): Add CAPADDR_SIMM7.
	(aarch64_print_operand): Add CAPADDR_SIMM7 and CAPADDR_SIMPLE.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_capaddr_simm7.
	* aarch64-tbl.h (QL1_A64C_CAPADDR, QL2_A64C_CA_CAPADDR): New
	macros.
	(aarch64_opcode_table): New instructions.
	(AARCH64_OPERANDS): New operands.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.