DesignWare GPIO port numbers are represented as unsized single-entry
regions. Use fdt_reg() to obtain the GPIO port number, rather than
requiring access to a region cell size specification stored in the
port group structure.
This allows the field name "regs" in the port group structure to be
repurposed to hold the I/O register base address, which then matches
the common usage in other drivers.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
dt_set_drvdata ( dt, group );
/* Map registers */
dt_set_drvdata ( dt, group );
/* Map registers */
- group->base = dt_ioremap ( dt, offset, 0, 0 );
- if ( ! group->base ) {
+ group->regs = dt_ioremap ( dt, offset, 0, 0 );
+ if ( ! group->regs ) {
rc = -ENODEV;
goto err_ioremap;
}
rc = -ENODEV;
goto err_ioremap;
}
- /* Get region cell size specification */
- fdt_reg_cells ( &sysfdt, offset, &group->regs );
-
/* Probe child ports */
if ( ( rc = dt_probe_children ( dt, offset ) ) != 0 )
goto err_children;
/* Probe child ports */
if ( ( rc = dt_probe_children ( dt, offset ) ) != 0 )
goto err_children;
dt_remove_children ( dt );
err_children:
dt_remove_children ( dt );
err_children:
- iounmap ( group->base );
+ iounmap ( group->regs );
err_ioremap:
free ( group );
err_alloc:
err_ioremap:
free ( group );
err_alloc:
dt_remove_children ( dt );
/* Unmap registers */
dt_remove_children ( dt );
/* Unmap registers */
- iounmap ( group->base );
+ iounmap ( group->regs );
/* Free device */
free ( group );
/* Free device */
free ( group );
group = dt_get_drvdata ( parent );
/* Identify port */
group = dt_get_drvdata ( parent );
/* Identify port */
- if ( ( rc = fdt_reg_address ( &sysfdt, offset, &group->regs, 0,
- &port ) ) != 0 ) {
+ if ( ( rc = fdt_reg ( &sysfdt, offset, &port ) ) != 0 ) {
DBGC ( dwgpio, "DWGPIO %s could not get port number: %s\n",
dwgpio->name, strerror ( rc ) );
goto err_port;
DBGC ( dwgpio, "DWGPIO %s could not get port number: %s\n",
dwgpio->name, strerror ( rc ) );
goto err_port;
dwgpio->name, parent->name, dwgpio->port, gpios->count );
/* Map registers */
dwgpio->name, parent->name, dwgpio->port, gpios->count );
/* Map registers */
- dwgpio->swport = ( group->base + DWGPIO_SWPORT ( port ) );
- dwgpio->ext = ( group->base + DWGPIO_EXT_PORT ( port ) );
+ dwgpio->swport = ( group->regs + DWGPIO_SWPORT ( port ) );
+ dwgpio->ext = ( group->regs + DWGPIO_EXT_PORT ( port ) );
dwgpio_dump ( dwgpio );
/* Record original register values */
dwgpio_dump ( dwgpio );
/* Record original register values */
/** A DesignWare GPIO port group */
struct dwgpio_group {
/** A DesignWare GPIO port group */
struct dwgpio_group {
- /** Register base */
- void *base;
- /** Region cell size specification */
- struct fdt_reg_cells regs;
+ /** Registers */
+ void *regs;
};
/** A DesignWare GPIO port */
};
/** A DesignWare GPIO port */