arm: socfpga: Enable ASYNC interrupts in Agilex SPL

Asynchronous aborts were previously masked at SPL
entry.

To ensure early detection of system errors
such as ECC faults or bus errors, asynchronous aborts
should be explicitly unmasked by clearing the A-bit in
the DAIF register during Agilex SPL initialization.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
# Conflicts:
#	arch/arm/mach-socfpga/spl_agilex.c

diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index 698e76f45b204747bffdbdbde3c5a1b2870d059a..2780e0f921f0510a31d63d8dee295a34e667c3ae 100644 (file)
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -43,6 +43,9 @@ void board_init_f(ulong dummy)
        int ret;
        struct udevice *dev;
 
+       /* Enable Async */
+       asm volatile("msr daifclr, #4");
+
 #if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
     spl_save_restore_data();
 #endif