[riscv] Maximise barrier effects of memory fences

The RISC-V "fence" instruction encoding includes bits for predecessor
and successor input and output operations, separate from read and
write operations.  It is up to the CPU implementation to decide what
counts as I/O space rather than memory space for the purposes of this
instruction.

Since we do not expect fencing to be performance-critical, keep
everything as simple and reliable as possible by using the unadorned
"fence" instruction (equivalent to "fence iorw, iorw").

Add a memory clobber to ensure that the compiler does not reorder the
barrier.  (The volatile qualifier seems to already prevent reordering
in practice, but this is not guaranteed according to the compiler
documentation.)

Signed-off-by: Michael Brown <mcb30@ipxe.org>

diff --git a/src/arch/riscv/include/ipxe/riscv_io.h b/src/arch/riscv/include/ipxe/riscv_io.h
index 8f903041816837e6829d87d66d921264bccb0bd7..be4449ff19cfc7da28a482c87ac61e44f3fa15ef 100644 (file)
--- a/src/arch/riscv/include/ipxe/riscv_io.h
+++ b/src/arch/riscv/include/ipxe/riscv_io.h
@@ -128,7 +128,7 @@ RISCV_WRITEX ( w, uint16_t, "h" );
  */
 static inline __always_inline void
 IOAPI_INLINE ( riscv, mb ) ( void ) {
-       __asm__ __volatile__ ( "fence rw, rw" );
+       __asm__ __volatile__ ( "fence" : : : "memory" );
 }
 
 /* Dummy PIO */