arm64: dts: mediatek: mt8188: Assign apll1 clock as parent to avoid hang

commit a69d5795f12b06d07b6437cafdd08f929fff2706 upstream.

Certain registers in the AFE IO space require the apll1 clock to be
enabled in order to be read, otherwise the machine hangs (registers like
0x280, 0x410 (AFE_GAIN1_CON0) and 0x830 (AFE_CONN0_5)). During AFE
driver probe, when initializing the regmap for the AFE IO space those
registers are read, resulting in a hang during boot.

This has been observed on the Genio 700 EVK, Genio 510 EVK and
MT8188-Geralt-Ciri Chromebook, all of which are based on the MT8188 SoC.

Assign CLK_TOP_APLL1_D4 as the parent for CLK_TOP_A1SYS_HP, which is
enabled during register read and write, to make sure the apll1 is
enabled during register operations and prevent the MT8188 machines from
hanging during boot.

Cc: stable@vger.kernel.org
Fixes: bd568ce198b8 ("arm64: dts: mediatek: mt8188: Add audio support")
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20250207-mt8188-afe-fix-hang-disabled-apll1-clk-v2-1-a636d844c272@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 23ec3ff6cad9b804ff97776ddab651ba092defa6..50f3c2b84be2bd50d262a89b481dbcc3e8df22ed 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1392,7 +1392,7 @@
                        compatible = "mediatek,mt8188-afe";
                        reg = <0 0x10b10000 0 0x10000>;
                        assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
-                       assigned-clock-parents =  <&clk26m>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>;
                        clocks = <&clk26m>,
                                 <&apmixedsys CLK_APMIXED_APLL1>,
                                 <&apmixedsys CLK_APMIXED_APLL2>,