arch: arm: mach-socfpga: Update kconfig for new platform Agilex7 M-series

Update Kconfig for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 850253f51cf1c42a2d33332d41e0683f3908b32a..e7257ff3e03a4e09ba74b75d74c05eac0deae82b 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -33,7 +33,7 @@ config COUNTER_FREQUENCY
                        ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
        default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
        default 100000000 if ARCH_ZYNQMP
-       default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
+       default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M
        default 0
        help
          For platforms with ARMv8-A and ARMv7-A which features a system

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 156cfbbcf3bc185fba48302cdf449f84c9894ec1..f2e959b5662464d70b1e7080009718341c6d2cf4 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -60,6 +60,18 @@ config TARGET_SOCFPGA_AGILEX
        select SPL_CLK if SPL
        select TARGET_SOCFPGA_SOC64
 
+config TARGET_SOCFPGA_AGILEX7M
+       bool
+       select ARMV8_MULTIENTRY
+       select ARMV8_SET_SMPEN
+       select BINMAN if SPL_ATF
+       select CLK
+       select FPGA_INTEL_SDM_MAILBOX
+       select GICV2
+       select NCORE_CACHE
+       select SPL_CLK if SPL
+       select TARGET_SOCFPGA_SOC64
+
 config TARGET_SOCFPGA_AGILEX5
        bool
        select BINMAN if SPL_ATF
@@ -149,6 +161,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK
        bool "Intel SOCFPGA SoCDK (Agilex)"
        select TARGET_SOCFPGA_AGILEX
 
+config TARGET_SOCFPGA_AGILEX7M_SOCDK
+       bool "Intel SOCFPGA SoCDK (Agilex7 M-series)"
+       select TARGET_SOCFPGA_AGILEX7M
+
 config TARGET_SOCFPGA_AGILEX5_SOCDK
        bool "Intel SOCFPGA SoCDK (Agilex5)"
        select TARGET_SOCFPGA_AGILEX5
@@ -226,6 +242,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
 endchoice
 
 config SYS_BOARD
+       default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK
        default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
        default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
@@ -248,6 +265,7 @@ config SYS_BOARD
        default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config SYS_VENDOR
+       default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK
        default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK
        default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "intel" if TARGET_SOCFPGA_N5X_SOCDK
@@ -271,6 +289,7 @@ config SYS_SOC
        default "socfpga"
 
 config SYS_CONFIG_NAME
+       default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK
        default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
        default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1