arm: socfpga: agilex: Probe DT for firewall setup

Update Agilex SPL code to implement device tree model
for firewall registers setup by using DTreg driver to
probe from device tree for the firewall settings instead
of calling firewall driver function.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index 4d7680455b774ac4480ca7848e1bd08ea8f9c54f..890ffc5f7c9e2dda7301f992649fab781322a172 100644 (file)
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -3,8 +3,10 @@
  * U-Boot additions
  *
  * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
+#include "socfpga_soc64_u-boot.dtsi"
 #include "socfpga_soc64_fit-u-boot.dtsi"
 
 /{
@@ -84,6 +86,79 @@
        bootph-all;
 };
 
+&socfpga_l3interconnect_firewall {
+       CCU_coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
+               reg = <0xf7100200 0x00000014>;
+               intel,offset-settings =
+                       /* Disable ocram security at CCU for non secure access */
+                       <0x0000004 0x8000ffff 0xe003ffff>,
+                       <0x0000008 0x8000ffff 0xe003ffff>,
+                       <0x000000c 0x8000ffff 0xe003ffff>,
+                       <0x0000010 0x8000ffff 0xe003ffff>;
+               bootph-all;
+       };
+
+       soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
+               reg = <0xf8020000 0x0000001c>;
+               intel,offset-settings =
+                       /* Disable MPFE firewall for SMMU */
+                       <0x00000000 0x00010101 0x00010101>,
+                       /* Disable MPFE firewall for HMC adapter */
+                       <0x00000004 0x00000001 0x00010101>;
+               bootph-all;
+       };
+
+       /*
+        * Below are all fpga2sdram firewall settings with default
+        * reset value for the sake of easy reference by users.
+        * Users may choose to remove any of these register
+        * configurations that they do not require in their specific
+        * implementation.
+        */
+       soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020100 {
+               reg = <0xf8020100 0x00000050>;
+               intel,offset-settings =
+                       <0x0000000 0x00000000 0x0000000f>,
+                       <0x0000004 0x00000000 0x0000000f>,
+                       <0x0000008 0x00000000 0x0000000f>,
+                       <0x0000010 0x00000000 0xffff0000>,
+                       <0x0000014 0x00000000 0x000000ff>,
+                       <0x0000018 0x00000000 0xffff0000>,
+                       <0x000001c 0x00000000 0x000000ff>,
+                       <0x0000020 0x00000000 0xffff0000>,
+                       <0x0000024 0x00000000 0x000000ff>,
+                       <0x0000028 0x00000000 0xffff0000>,
+                       <0x000002c 0x00000000 0x000000ff>,
+                       <0x0000030 0x00000000 0xffff0000>,
+                       <0x0000034 0x00000000 0x000000ff>,
+                       <0x0000038 0x00000000 0xffff0000>,
+                       <0x000003c 0x00000000 0x000000ff>,
+                       <0x0000040 0x00000000 0xffff0000>,
+                       <0x0000044 0x00000000 0x000000ff>,
+                       <0x0000048 0x00000000 0xffff0000>,
+                       <0x000004c 0x00000000 0x000000ff>;
+               bootph-all;
+       };
+
+       /*
+        * Example of ccu_mem0_I_main QOS settings with
+        * default reset value for the sake of easy reference
+        * by users. Users may choose to remove any of these register
+        * configurations that they do not require in their specific
+        * implementation.
+        */
+       soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {
+               reg = <0xf8022080 0x0000001c>;
+               intel,offset-settings =
+                       <0x0000008 0x00000200 0x00000303>,
+                       <0x000000c 0x00000003 0x00000003>,
+                       <0x0000010 0x00000BFE 0x00007fff>,
+                       <0x0000014 0x00000008 0x000003ff>,
+                       <0x0000018 0x00000000 0x0000000f>;
+               bootph-all;
+       };
+};
+
 &sysmgr {
        compatible = "altr,sys-mgr", "syscon";
        bootph-all;

diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
new file mode 100644 (file)
index 0000000..0164d1a
--- /dev/null
+++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+/ {
+       soc {
+               socfpga-system-mgr-firewall {
+                       compatible = "intel,socfpga-dtreg";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       bootph-all;
+
+                       i_sys_mgr_core@ffd12000 {
+                               reg = <0xffd12000 0x00000230>;
+                               intel,offset-settings =
+                                       /* Enable non-secure interface to DMA */
+                                       <0x00000020 0xff010000 0xff010011>,
+                                       /* Enable non-secure interface to DMA periph */
+                                       <0x00000024 0xffffffff 0xffffffff>;
+                               bootph-all;
+                       };
+               };
+
+               socfpga_l3interconnect_firewall:socfpga-l3interconnect-firewall {
+                       compatible = "intel,socfpga-dtreg";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       bootph-all;
+
+                       noc_fw_l4_per_l4_per_scr@ffd21000 {
+                               reg = <0xffd21000 0x00000074>;
+                               intel,offset-settings =
+                                       /* Disable L4 periphs firewall */
+                                       <0x00000000 0x01010001 0x01010001>,
+                                       <0x00000004 0x01010001 0x01010001>,
+                                       <0x0000000c 0x01010001 0x01010001>,
+                                       <0x00000010 0x01010001 0x01010001>,
+                                       <0x0000001c 0x01010001 0x01010101>,
+                                       <0x00000020 0x01010001 0x01010101>,
+                                       <0x00000024 0x01010001 0x01010101>,
+                                       <0x00000028 0x01010001 0x01010101>,
+                                       <0x0000002c 0x01010001 0x01010001>,
+                                       <0x00000030 0x01010001 0x01010001>,
+                                       <0x00000034 0x01010001 0x01010001>,
+                                       <0x00000040 0x01010001 0x01010001>,
+                                       <0x00000044 0x01010001 0x01010101>,
+                                       <0x00000048 0x01010001 0x01010101>,
+                                       <0x00000050 0x01010001 0x01010101>,
+                                       <0x00000054 0x01010001 0x01010101>,
+                                       <0x00000058 0x01010001 0x01010101>,
+                                       <0x0000005c 0x01010001 0x01010101>,
+                                       <0x00000060 0x01010001 0x01010101>,
+                                       <0x00000064 0x01010001 0x01010101>,
+                                       <0x00000068 0x01010001 0x01010101>,
+                                       <0x0000006c 0x01010001 0x01010101>,
+                                       <0x00000070 0x01010001 0x01010101>;
+                               bootph-all;
+                       };
+
+                       noc_fw_l4_sys_l4_sys_scr@ffd21100 {
+                               reg = <0xffd21100 0x00000098>;
+                               intel,offset-settings =
+                                       /* Disable L4 system firewall */
+                                       <0x00000008 0x01010001 0x01010001>,
+                                       <0x0000000c 0x01010001 0x01010001>,
+                                       <0x00000010 0x01010001 0x01010001>,
+                                       <0x00000014 0x01010001 0x01010001>,
+                                       <0x00000018 0x01010001 0x01010001>,
+                                       <0x0000001c 0x01010001 0x01010001>,
+                                       <0x00000020 0x01010001 0x01010001>,
+                                       <0x0000002c 0x01010001 0x01010001>,
+                                       <0x00000030 0x01010001 0x01010001>,
+                                       <0x00000034 0x01010001 0x01010001>,
+                                       <0x00000038 0x01010001 0x01010001>,
+                                       <0x00000040 0x01010001 0x01010001>,
+                                       <0x00000044 0x01010001 0x01010001>,
+                                       <0x00000048 0x01010001 0x01010001>,
+                                       <0x0000004c 0x01010001 0x01010001>,
+                                       <0x00000054 0x01010001 0x01010001>,
+                                       <0x00000058 0x01010001 0x01010001>,
+                                       <0x0000005c 0x01010001 0x01010001>,
+                                       <0x00000060 0x01010001 0x01010101>,
+                                       <0x00000064 0x01010001 0x01010101>,
+                                       <0x00000068 0x01010001 0x01010101>,
+                                       <0x0000006c 0x01010001 0x01010101>,
+                                       <0x00000070 0x01010001 0x01010101>,
+                                       <0x00000074 0x01010001 0x01010101>,
+                                       <0x00000078 0x01010001 0x03010001>,
+                                       <0x00000090 0x01010001 0x01010001>,
+                                       <0x00000094 0x01010001 0x01010001>;
+                               bootph-all;
+                       };
+
+                       noc_fw_soc2fpga_soc2fpga_scr@ffd21200 {
+                               reg = <0xffd21200 0x00000004>;
+                               /* Disable soc2fpga security access */
+                               intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
+                               bootph-all;
+                       };
+
+                       noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 {
+                               reg = <0xffd21300 0x00000004>;
+                               /* Disable lightweight soc2fpga security access */
+                               intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
+                               bootph-all;
+                       };
+
+                       noc_fw_tcu_tcu_scr@ffd21400 {
+                               reg = <0xffd21400 0x00000004>;
+                               /* Disable DMA ECC security access, for SMMU use */
+                               intel,offset-settings = <0x00000000 0x01010001 0x01010001>;
+                               bootph-all;
+                       };
+
+                       noc_fw_priv_MemoryMap_priv@ffd24800 {
+                               reg = <0xffd24800 0x0000000c>;
+                               intel,offset-settings =
+                               /* Enable non-prviledged access to various periphs */
+                                       <0x00000000 0xfff73ffb 0xfff73ffb>;
+                               bootph-all;
+                       };
+               };
+
+               socfpga_smmu_secure_config: socfpga-smmu-secure-config {
+                       compatible = "intel,socfpga-dtreg";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       bootph-all;
+
+                       /* TCU */
+                       noc_fw_tcu_tcu_scr@ffd21400 {
+                               reg = <0xffd21400 0x00000004>;
+                               intel,offset-settings =
+                                       <0x00000000 0x01010001 0x01010001>;
+                               bootph-all;
+                       };
+
+                       /* System manager */
+                       i_sys_mgt_sysmgr_csr@ffd12000 {
+                               reg = <0xffd12000 0x00000500>;
+                               intel,offset-settings =
+                                       /* i_sys_mgr_core_emac0 */
+                                       <0x00000044 0x0a000000 0xffff0103>,
+                                       /* i_sys_mgr_core_emac1 */
+                                       <0x00000048 0x0a000000 0xffff0103>,
+                                       /* i_sys_mgr_core_emac2 */
+                                       <0x0000004c 0x0a000000 0xffff0103>,
+                                       /* i_sys_mgr_core_nand_l3master */
+                                       <0x00000034 0x00220000 0x007733ff>,
+                                       /* i_sys_mgr_core_sdmmc_l3master */
+                                       <0x0000002c 0x00000020 0x03ff03ff>,
+                                       /* i_sys_mgr_core_usb0_l3master */
+                                       <0x00000038 0x00000200 0x03ff30ff>,
+                                       /* i_sys_mgr_core_usb1_l3master */
+                                       <0x0000003c 0x00000200 0x03ff30ff>;
+                               bootph-all;
+                       };
+               };
+       };
+};

diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index 91c27a5543d61004bf1feb679d6a05bda2d0e5c6..faba04338387115bc25f2b84e1b7ca7443a3de12 100644 (file)
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -66,7 +66,18 @@ void board_init_f(ulong dummy)
        print_reset_info();
        cm_print_clock_quick_summary();
 
-       firewall_setup();
+       ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev);
+       if (ret) {
+               printf("System manager firewall configuration failed: %d\n", ret);
+               hang();
+       }
+
+       ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev);
+       if (ret) {
+               printf("L3 interconnect firewall configuration failed: %d\n", ret);
+               hang();
+       }
+
        ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
        if (ret) {
                debug("CCU init failed: %d\n", ret);