Bug 498421 - s390x: Add BPP, BPRP, and NIAI insns

Add support for the branch prediction preload (BPP), branch prediction
relative preload (BPRP), and next instruction access intent (NIAI)
instructions.  These instructions just provide performance hints to the
CPU and have no other effect on program execution.  Thus implement them as
no-ops.

diff --git a/NEWS b/NEWS
index 7145157f2112d3b7d2b041a98ca58a57b2f5a463..b2036da737c66dae4098ba29ce8028e335f592a8 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -54,6 +54,7 @@ are not entered into bugzilla tend to get forgotten about or ignored.
 498143  False positive on EVIOCGRAB ioctl
 498317  FdBadUse is not a valid CoreError type in a suppression
         even though it's generated by --gen-suppressions=yes
+498421  s390x: support BPP, BPRP and NIAI insns
 498422  s390x: Fix VLRL and VSTRL insns
 498492  none/tests/amd64/lzcnt64 crashes on FreeBSD compiled with clang
 498629  s390x: Fix S[L]HHHR and S[L]HHLR insns

diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index b870b77fe472eb667af8c45a9e63c1ee812b7ec0..5b160021032d4db6c4816b3a6af16bcc5446cd73 100644 (file)
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -104,6 +104,11 @@ typedef enum {
 /*------------------------------------------------------------*/
 
 #define I_i(insn) ((insn) & 0xff)
+#define IE_i1(insn) (((insn) >> 4) & 0xf)
+#define IE_i2(insn) ((insn) & 0xf)
+#define MII_m1(insn) (((insn) >> 52) & 0xf)
+#define MII_i2(insn) (((insn) >> 40) & 0xfff)
+#define MII_i3(insn) (((insn) >> 16) & 0xffffff)
 #define RR_r1(insn) (((insn) >> 4) & 0xf)
 #define RR_r2(insn) ((insn) & 0xf)
 #define RI_r1(insn) (((insn) >> 20) & 0xf)
@@ -143,6 +148,10 @@ typedef enum {
 #define SI_i2(insn) (((insn) >> 16) & 0xff)
 #define SI_b1(insn) (((insn) >> 12) & 0xf)
 #define SI_d1(insn) ((insn) & 0xfff)
+#define SMI_m1(insn) (((insn) >> 52) & 0xf)
+#define SMI_b3(insn) (((insn) >> 44) & 0xf)
+#define SMI_d3(insn) (((insn) >> 32) & 0xfff)
+#define SMI_i2(insn) (((insn) >> 16) & 0xffff)
 #define RIE_r1(insn) (((insn) >> 52) & 0xf)
 #define RIE_r3(insn) (((insn) >> 48) & 0xf)
 #define RIE_i2(insn) (((insn) >> 32) & 0xffff)
@@ -2741,6 +2750,16 @@ s390_format_I(const HChar *(*irgen)(UChar i),
       S390_DISASM(MNM(mnm), UINT(i));
 }
 
+static void
+s390_format_IE(const HChar *(*irgen)(UChar i1, UChar i2),
+               UChar i1, UChar i2)
+{
+   const HChar *mnm = irgen(i1, i2);
+
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
+      S390_DISASM(MNM(mnm), UINT(i1), UINT(i2));
+}
+
 static void
 s390_format_E(const HChar *(*irgen)(void))
 {
@@ -2750,6 +2769,19 @@ s390_format_E(const HChar *(*irgen)(void))
       S390_DISASM(MNM(mnm));
 }
 
+static void
+s390_format_MII_UPP(const HChar *(*irgen)(UChar m1, UShort i2, UShort i3),
+                    UChar m1, UShort i2, UShort i3)
+{
+   const HChar *mnm;
+
+   mnm = irgen(m1, i2, i3);
+
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
+      S390_DISASM(MNM(mnm), UINT(m1), PCREL((Int)((Short)(i2 << 4) >> 4)),
+                  PCREL((Int)(Short)i3));
+}
+
 static void
 s390_format_RI(const HChar *(*irgen)(UChar r1, UShort i2),
                UChar r1, UShort i2)
@@ -3653,6 +3685,22 @@ s390_format_SIY_IRD(const HChar *(*irgen)(UChar i2, IRTemp op1addr),
       S390_DISASM(MNM(mnm), SDXB(dh1, dl1, 0, b1), INT((Int)(Char)i2));
 }
 
+static void
+s390_format_SMI_U0RDP(const HChar *(*irgen)(UChar m1, UShort i2, IRTemp op3addr),
+                      UChar m1, UShort i2, UChar b3, UShort d3)
+{
+   const HChar *mnm;
+   IRTemp op3addr = newTemp(Ity_I64);
+
+   assign(op3addr,
+          binop(Iop_Add64, mkU64(d3), b3 != 0 ? get_gpr_dw0(b3) : mkU64(0)));
+
+   mnm = irgen(m1, i2, op3addr);
+
+   if (UNLIKELY(vex_traceflags & VEX_TRACE_FE))
+      S390_DISASM(MNM(mnm), UINT(m1), PCREL((Int)(Short)i2), UDXB(d3, 0, b3));
+}
+
 static void
 s390_format_SS_L0RDRD(const HChar *(*irgen)(UChar, IRTemp, IRTemp),
                       UChar l, UChar b1, UShort d1, UChar b2, UShort d2)
@@ -20307,6 +20355,27 @@ s390_irgen_KDSA(UChar r1, UChar r2)
    return "kdsa";
 }
 
+static const HChar *
+s390_irgen_BPP(UChar m1, UShort i2, IRTemp op3addr)
+{
+   /* Treat as a no-op */
+   return "bpp";
+}
+
+static const HChar *
+s390_irgen_BPRP(UChar m1, UShort i2, UShort i3)
+{
+   /* Treat as a no-op */
+   return "bprp";
+}
+
+static const HChar *
+s390_irgen_NIAI(UChar i1, UChar i2)
+{
+   /* Treat as a no-op */
+   return "niai";
+}
+
 /* New insns are added here.
    If an insn is contingent on a facility being installed also
    check whether function do_extension_STFLE needs updating. */
@@ -20667,7 +20736,8 @@ s390_decode_4byte_and_irgen(const UChar *bytes)
    case 0xb2ec: /* ETND */ goto unimplemented;
    case 0xb2ed: /* ECPGA */ goto unimplemented;
    case 0xb2f8: /* TEND */ goto unimplemented;
-   case 0xb2fa: /* NIAI */ goto unimplemented;
+   case 0xb2fa: s390_format_IE(s390_irgen_NIAI, IE_i1(ovl),
+                               IE_i2(ovl));  goto ok;
    case 0xb2fc: /* TABORT */ goto unimplemented;
    case 0xb2ff: /* TRAP4 */ goto unimplemented;
    case 0xb300: s390_format_RRE_FF(s390_irgen_LPEBR, RRE_r1(ovl),
@@ -23295,8 +23365,10 @@ s390_decode_6byte_and_irgen(const UChar *bytes)
    }
 
    switch (((ovl >> 16) & 0xff0000000000ULL) >> 40) {
-   case 0xc5ULL: /* BPRP */ goto unimplemented;
-   case 0xc7ULL: /* BPP */ goto unimplemented;
+   case 0xc5ULL: s390_format_MII_UPP(s390_irgen_BPRP, MII_m1(ovl), MII_i2(ovl),
+                                     MII_i3(ovl));  goto ok;
+   case 0xc7ULL: s390_format_SMI_U0RDP(s390_irgen_BPP, SMI_m1(ovl), SMI_i2(ovl),
+                                       SMI_b3(ovl), SMI_d3(ovl));  goto ok;
    case 0xd0ULL: /* TRTR */ goto unimplemented;
    case 0xd1ULL: /* MVN */ goto unimplemented;
    case 0xd2ULL: s390_format_SS_L0RDRD(s390_irgen_MVC, SS_l(ovl),

diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv
index 75baaf15ad31f06cf748df2203428c6bbcf4c613..e2d69fc996f4a152b6feb10e6d1e129602ab1ed3 100644 (file)
--- a/docs/internals/s390-opcodes.csv
+++ b/docs/internals/s390-opcodes.csv
@@ -963,10 +963,10 @@ tabort,"transaction abort","not implemented",zEC12,
 tbegin,"transaction begin","not implemented",zEC12,
 tbeginc,"constrained transaction begin","not implemented",zEC12,
 tend,"transaction end","not implemented",zEC12,
-bpp,"branch prediction preload","not implemented",zEC12,
-bprp,"branch prediction relative preload","not implemented",zEC12,
+bpp,"branch prediction preload",implemented,zEC12,
+bprp,"branch prediction relative preload",implemented,zEC12,
 ppa,"perform processor assist","not implemented",zEC12,
-niai,"next instruction access intent","not implemented",zEC12,
+niai,"next instruction access intent",implemented,zEC12,
 crdte,"compare and replace DAT table entry",N/A,"privileged instruction"
 lat,"load and trap 32 bit",implemented,zEC12,
 lgat,"load and trap 64 bit",implemented,zEC12,

diff --git a/none/tests/s390x/disasm-test/opcode.c b/none/tests/s390x/disasm-test/opcode.c
index 8bd53dae9c386fd667ac5c158d3eb5a913ee2195..993a1fb05081724423b6273ad39d8a47068f9fd8 100644 (file)
--- a/none/tests/s390x/disasm-test/opcode.c
+++ b/none/tests/s390x/disasm-test/opcode.c
@@ -228,9 +228,8 @@ static const char *opcodes[] = {
    "bxle   r1,r3,d12(b2)",
    "bxleg  r1,r3,d20(b2)",
 
-// FIXME TBD   "bpp    m1,ri2:s16,d12(b3)", // exhi
-// FIXME TBD   "bprp   m1,ri2:s12,ri3:s24", // exhi
-
+   "bpp    i1:u4,ri2:s16,d12(b3)",  // exhi
+   "bprp   i1:u4,ri2:s12,ri3:s24",  // exhi
    "bras   r1,ri2:s16",
    "brasl  r1,ri2:s32",
 
@@ -694,7 +693,7 @@ static const char *opcodes[] = {
    "nnrk   r1,r2,r3",           // mi3
    "nngrk  r1,r2,r3",           // mi3
 
-// FIXME TBD   niai    i1:u4{0:3},i2:u4{0:3}  // exhi   no spec. exc. for i1,i2
+   "niai   i1:u4,i2:u4",        // exhi
 
    // ntstg not implemented