[riscv] Add fences around early UART writes

Add a fence between the write to the UART transmit register and the
subsequent read from the transmit status register, to ensure that the
status correctly reflects the occurrence of the write.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

diff --git a/src/arch/riscv/prefix/libprefix.S b/src/arch/riscv/prefix/libprefix.S
index 583f2711703a3cc02b56eb16311b941c3f2ebfb2..3fe01d7c853183f6abd1660aca4c5a349d7345fd 100644 (file)
--- a/src/arch/riscv/prefix/libprefix.S
+++ b/src/arch/riscv/prefix/libprefix.S
@@ -204,6 +204,7 @@ early_uart_reg_base_64_done_\@:
        .macro  print_char_uart_8250
        early_uart_reg_base a7
        sb      a0, EARLY_UART_8250_TX(a7)
+       fence
 early_uart_8250_wait_\@:
        lbu     a1, EARLY_UART_8250_LSR(a7)
        andi    a1, a1, EARLY_UART_8250_LSR_THRE
@@ -236,6 +237,7 @@ early_uart_8250_wait_\@:
        .macro  print_char_uart_sifive
        early_uart_reg_base a7
        sw      a0, EARLY_UART_SIFIVE_TXFIFO(a7)
+       fence
 early_uart_sifive_wait_\@:
        lw      a1, EARLY_UART_SIFIVE_TXFIFO(a7)
        bltz    a1, early_uart_sifive_wait_\@