#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
-#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d
+#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524D
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
#define SOC64_HANDOFF_MAGIC_PERI 0x50455249
#else
#define SOC64_HANDOFF_SIZE 4096
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
- IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
#define SOC64_HANDOFF_BASE 0xFFE3F000
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x634)
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_DDR_LEN 5
+#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0)
+#define SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK BIT(0)
+#else
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#endif
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
#define SOC64_HANDOFF_BASE 0x0007F000
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)