]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arch: arm: mach-socfpga: Add Agilex7 M-series mach-socfgpa enablement
authorTingting Meng <tingting.meng@altera.com>
Mon, 4 Aug 2025 01:24:49 +0000 (18:24 -0700)
committerTien Fong Chee <tien.fong.chee@intel.com>
Fri, 8 Aug 2025 14:20:51 +0000 (22:20 +0800)
Add platform related files for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arch/arm/mach-socfpga/include/mach/misc.h
arch/arm/mach-socfpga/spl_agilex7m.c [new file with mode: 0644]
board/intel/agilex7m-socdk/MAINTAINERS
board/intel/agilex7m-socdk/socfpga.c [new file with mode: 0644]

index b200c877d43020b3ac5ca11543b28570b930cad3..0b80e95213175a7abc25e31c62870bb0863a3bac 100644 (file)
@@ -41,7 +41,8 @@ void socfpga_sdram_remap_zero(void);
 #endif
 
 #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
-       defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+       defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+       defined(CONFIG_TARGET_SOCFPGA_AGILEX7M)
 int is_fpga_config_ready(void);
 #endif
 
diff --git a/arch/arm/mach-socfpga/spl_agilex7m.c b/arch/arm/mach-socfpga/spl_agilex7m.c
new file mode 100644 (file)
index 0000000..90065cc
--- /dev/null
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <wdt.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+       int ret;
+       struct udevice *dev;
+
+       /* Enable Async */
+       asm volatile("msr daifclr, #4");
+
+#ifdef CONFIG_XPL_BUILD
+       spl_save_restore_data();
+#endif
+
+       ret = spl_early_init();
+       if (ret)
+               hang();
+
+       socfpga_get_sys_mgr_addr();
+       socfpga_get_managers_addr();
+
+       /* Ensure watchdog is paused when debugging is happening */
+       writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+              socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+       /* ensure all processors are not released prior Linux boot */
+       writeq(0, CPU_RELEASE_ADDR);
+
+       timer_init();
+
+       mbox_init();
+
+       mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
+
+       sysmgr_pinmux_init();
+
+       ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+       if (ret) {
+               debug("Clock init failed: %d\n", ret);
+               hang();
+       }
+
+       /*
+        * Enable watchdog as early as possible before initializing other
+        * component. Watchdog need to be enabled after clock driver because
+        * it will retrieve the clock frequency from clock driver.
+        */
+       if (CONFIG_IS_ENABLED(WDT))
+               initr_watchdog();
+
+       preloader_console_init();
+       print_reset_info();
+       cm_print_clock_quick_summary();
+
+       ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev);
+       if (ret) {
+               printf("System manager firewall configuration failed: %d\n", ret);
+               hang();
+       }
+
+       ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev);
+       if (ret) {
+               printf("L3 interconnect firewall configuration failed: %d\n", ret);
+               hang();
+       }
+
+       ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
+       if (ret) {
+               debug("CCU init failed: %d\n", ret);
+               hang();
+       }
+
+       if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) {
+               ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+               if (ret) {
+                       debug("DRAM init failed: %d\n", ret);
+                       hang();
+               }
+       }
+
+       if (IS_ENABLED(CONFIG_CADENCE_QSPI))
+               mbox_qspi_open();
+}
index d69e614a0bee0e4b86f5df9be30e509b3bcf053e..9a5b80ae4dfe7b361eaf4f7ffed242c87b4854e2 100644 (file)
@@ -4,6 +4,7 @@ M:      Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
 S:     Maintained
 F:     arch/arm/dts/socfpga_soc64_u-boot.dtsi
 F:     arch/arm/dts/socfpga_agilex7m*
+F:     arch/arm/mach-socfpga/spl_agilex7m.c
 F:     board/intel/agilex7m-socdk/
 F:     include/configs/socfpga_agilex7m_socdk.h
 F:     configs/socfpga_agilex7m_sdmmc_defconfig
diff --git a/board/intel/agilex7m-socdk/socfpga.c b/board/intel/agilex7m-socdk/socfpga.c
new file mode 100644 (file)
index 0000000..60c8704
--- /dev/null
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include <asm/arch/misc.h>
+
+int board_early_init_f(void)
+{
+       socfpga_get_sys_mgr_addr();
+       return 0;
+}