RISC-V: Support -march=unset

This patch introduces a new `-march=unset` option for RISC-V GCC that
allows users to explicitly ignore previous `-march` options and derive
the architecture string from the `-mcpu` option instead.

This feature is particularly useful for build systems and toolchain
configurations where you want to ensure the architecture is always
derived from the CPU specification rather than relying on potentially
conflicting `-march` options.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_expand_arch):
	Ignore `unset`.
	* config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Handle
	`-march=unset`.
	(ARCH_UNSET_CLEANUP_SPECS): New.
	(DRIVER_SELF_SPECS): Handle -march=unset.
	* doc/invoke.texi (RISC-V Options): Update documentation for
	`-march=unset`.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-unset-1.c: New test.
	* gcc.target/riscv/arch-unset-2.c: New test.
	* gcc.target/riscv/arch-unset-3.c: New test.
	* gcc.target/riscv/arch-unset-4.c: New test.
	* gcc.target/riscv/arch-unset-5.c: New test.

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index da3cb9f788dc887cbc2968201a095c8e72c4396d..f2ede074ac5877dcd22b90946de06840b5ec9295 100644 (file)
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1758,6 +1758,11 @@ riscv_expand_arch (int argc,
 {
   gcc_assert (argc == 1);
   location_t loc = UNKNOWN_LOCATION;
+
+  /* Filter out -march=unset, it will expand from -mcpu later.  */
+  if (strcmp (argv[0], "unset") == 0)
+    return "";
+
   /* Try to interpret the arch as CPU first.  */
   const char *arch_str = riscv_expand_arch_from_cpu (argc, argv);
   if (!strlen (arch_str))

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 45fa521f219f1f5f88ccf8c1c09ebb04aeb7f68f..29342d8a64cf9c79c9f0ce35a10bbb9e14bc6431 100644 (file)
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -71,7 +71,7 @@ extern const char *riscv_arch_help (int argc, const char **argv);
   {"tune", "%{!mtune=*:"                                               \
           "  %{!mcpu=*:-mtune=%(VALUE)}"                               \
           "  %{mcpu=*:-mtune=%:riscv_default_mtune(%* %(VALUE))}}" },  \
-  {"arch", "%{!march=*:"                                               \
+  {"arch", "%{!march=*|march=unset:"                                   \
           "  %{!mcpu=*:-march=%(VALUE)}"                               \
           "  %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" },  \
   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" },                               \
@@ -111,13 +111,19 @@ extern const char *riscv_arch_help (int argc, const char **argv);
 %(subtarget_asm_spec)" \
 ASM_MISA_SPEC
 
+/* Drop all -march=* options before -march=unset.  */
+#define ARCH_UNSET_CLEANUP_SPECS  \
+  "%{march=unset:%<march=*} "  \
+
 #undef DRIVER_SELF_SPECS
 #define DRIVER_SELF_SPECS                                      \
+ARCH_UNSET_CLEANUP_SPECS \
 "%{march=help:%:riscv_arch_help()} "                           \
 "%{print-supported-extensions:%:riscv_arch_help()} "           \
 "%{-print-supported-extensions:%:riscv_arch_help()} "          \
 "%{march=*:%:riscv_expand_arch(%*)} "                          \
-"%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
+"%{!march=*|march=unset:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} " \
+"%{march=unset:%{!mcpu=*:%eAt least one valid -mcpu option must be given after -march=unset}} "
 
 #define LOCAL_LABEL_PREFIX     "."
 #define USER_LABEL_PREFIX      ""

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 105a60d849f5dc9e6d2e99555962ac22636dc5d6..bc5b3e0b75abe691bd37b606749db1c203a71ee7 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31336,7 +31336,7 @@ The default is @option{-misa-spec=20191213} unless GCC has been configured
 with @option{--with-isa-spec=} specifying a different default version.
 
 @opindex march
-@item -march=@var{ISA-string|Profiles|Profile_ISA-string}
+@item -march=@var{ISA-string|Profiles|Profile_ISA-string|help|unset}
 Generate code for given RISC-V ISA or Profiles or a combination of them
 (e.g.@: @samp{rv64im} @samp{rvi20u64} @samp{rvi20u64_zbb}).  ISA strings and
 Profiles must be lower-case.  Examples include @samp{rv64i}, @samp{rv32g},
@@ -31347,6 +31347,12 @@ at the beginning of the option, then use underline connect ISA-string (e.g.@:
 @option{help} (@option{-march=help}) is accepted to list all supported
 extensions.
 
+@samp{-march=unset} causes the compiler to ignore any @samp{-march=@dots{}} options
+that appear earlier on the command line, behaving as if the option was never
+passed. This is useful for ensuring that the architecture is taken from the
+@samp{-mcpu} option, and it will result in an error if no @samp{-mcpu} option
+is given when @samp{-march=unset} is used.
+
 The syntax of the ISA string is defined as follows:
 
 @table @code

diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-1.c b/gcc/testsuite/gcc.target/riscv/arch-unset-1.c
new file mode 100644 (file)
index 0000000..971b936
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-unset-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -mabi=lp64 -misa-spec=20191213" } */
+int foo()
+{
+}
+
+/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0\"" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-2.c b/gcc/testsuite/gcc.target/riscv/arch-unset-2.c
new file mode 100644 (file)
index 0000000..9840658
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-unset-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=rv64i -mabi=lp64 -misa-spec=20191213" } */
+int foo()
+{
+}
+
+/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1\"" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-3.c b/gcc/testsuite/gcc.target/riscv/arch-unset-3.c
new file mode 100644 (file)
index 0000000..5ddc224
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-unset-3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=rv64i -march=unset -mabi=lp64 -misa-spec=20191213" } */
+int foo()
+{
+}
+
+/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0\"" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-4.c b/gcc/testsuite/gcc.target/riscv/arch-unset-4.c
new file mode 100644 (file)
index 0000000..c16821d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-unset-4.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=unset -march=rv64i -march=unset -march=rv64i -mabi=lp64 -misa-spec=20191213" } */
+int foo()
+{
+}
+
+/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1\"" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-5.c b/gcc/testsuite/gcc.target/riscv/arch-unset-5.c
new file mode 100644 (file)
index 0000000..368c129
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-unset-5.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i -march=unset -mabi=lp64 -misa-spec=20191213" } */
+int foo()
+{
+}
+
+/* { dg-error "At least one valid -mcpu option must be given after -march=unset" "" { target { "riscv*-*-*" } } 0 } */