]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arch: arm: dts: agilex: Update Agilex device tree
authorAlif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Mon, 4 Aug 2025 01:24:30 +0000 (18:24 -0700)
committerTien Fong Chee <tien.fong.chee@intel.com>
Fri, 8 Aug 2025 08:00:45 +0000 (16:00 +0800)
Update exisitng Agilex device tree to support multiple flashes boot
- MMC, QSPI and NAND.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
MAINTAINERS
arch/arm/dts/socfpga_agilex.dtsi
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
arch/arm/dts/socfpga_agilex_socdk.dts

index 43175819230c140bc6cb5d04bf0ed445cef4c26e..fdce820c7925391899b317f75f35659f79a031a4 100644 (file)
@@ -154,10 +154,11 @@ M:        Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
 M:     Tien Fong Chee <tien.fong.chee@altera.com>
 S:     Maintained
 T:     git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
+F:     arch/arm/dts/socfpga_*
+F:     arch/arm/mach-socfpga/
 F:     configs/socfpga_*
 F:     drivers/ddr/altera/
 F:     drivers/power/domain/altr-pmgr-agilex5.c
-F:     arch/arm/mach-socfpga/
 F:     drivers/sysreset/sysreset_socfpga*
 
 ARM AMLOGIC SOC SUPPORT
index 712304d07a496a4e65d10db1e860e02c2685d439..be5100aea983dda5bfb0ca65013d77090db54990 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier:     GPL-2.0
 /*
  * Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 /dts-v1/;
                              <0xffb80000 0x1000>;
                        reg-names = "nand_data", "denali_reg";
                        interrupts = <0 97 4>;
+                       clocks = <&clkmgr AGILEX_NAND_CLK>,
+                                <&clkmgr AGILEX_NAND_X_CLK>;
+                       clock-names = "nand", "nand_x";
                        resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
                        status = "disabled";
                };
index 63df28e83649f7ea8f987a2b5525f5c1f0da5d50..f9491d570686a8a671b57e20f012806713cf4e24 100644 (file)
@@ -3,11 +3,17 @@
  * U-Boot additions
  *
  * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #include "socfpga_agilex-u-boot.dtsi"
 
 /{
+       chosen {
+               stdout-path = "serial0:115200n8";
+               u-boot,spl-boot-order = &mmc,&flash0,&nand;
+       };
+
        aliases {
                spi0 = &qspi;
                i2c0 = &i2c1;
        spi-tx-bus-width = <4>;
        spi-rx-bus-width = <4>;
        bootph-all;
+       /delete-property/ cdns,read-delay;
 };
 
 &i2c1 {
        status = "okay";
 };
 
+&nand {
+       status = "okay";
+       nand-bus-width = <16>;
+       bootph-all;
+};
+
 &mmc {
        drvsel = <3>;
        smplsel = <0>;
@@ -53,3 +66,9 @@
 &watchdog0 {
        bootph-all;
 };
+
+#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
+&binman {
+       /delete-node/ kernel;
+};
+#endif
index bcdeecc0e024e997fe24f4ee3f2177a7f61a6536..9cb9ff9fbc066d1465b9bbf8f881b8b7795504f6 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier:     GPL-2.0
 /*
  * Copyright (C) 2019, Intel Corporation
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 #include "socfpga_agilex.dtsi"
 
                ethernet2 = &gmac2;
        };
 
-       chosen {
-               stdout-path = "serial0:115200n8";
-       };
-
        leds {
                compatible = "gpio-leds";
                hps0 {
                        #size-cells = <1>;
 
                        qspi_boot: partition@0 {
-                               label = "Boot and fpga data";
-                               reg = <0x0 0x034B0000>;
+                               label = "u-boot";
+                               reg = <0x0 0x04200000>;
                        };
 
-                       qspi_rootfs: partition@34B0000 {
-                               label = "Root Filesystem - JFFS2";
-                               reg = <0x034B0000 0x0EB50000>;
+                       root: partition@4200000 {
+                               label = "root";
+                               reg = <0x04200000 0x0BE00000>;
                        };
                };
        };