M: Tien Fong Chee <tien.fong.chee@altera.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
+F: arch/arm/dts/socfpga_*
+F: arch/arm/mach-socfpga/
F: configs/socfpga_*
F: drivers/ddr/altera/
F: drivers/power/domain/altr-pmgr-agilex5.c
-F: arch/arm/mach-socfpga/
F: drivers/sysreset/sysreset_socfpga*
ARM AMLOGIC SOC SUPPORT
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
/dts-v1/;
<0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 97 4>;
+ clocks = <&clkmgr AGILEX_NAND_CLK>,
+ <&clkmgr AGILEX_NAND_X_CLK>;
+ clock-names = "nand", "nand_x";
resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
status = "disabled";
};
* U-Boot additions
*
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_agilex-u-boot.dtsi"
/{
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &mmc,&flash0,&nand;
+ };
+
aliases {
spi0 = &qspi;
i2c0 = &i2c1;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
bootph-all;
+ /delete-property/ cdns,read-delay;
};
&i2c1 {
status = "okay";
};
+&nand {
+ status = "okay";
+ nand-bus-width = <16>;
+ bootph-all;
+};
+
&mmc {
drvsel = <3>;
smplsel = <0>;
&watchdog0 {
bootph-all;
};
+
+#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
+&binman {
+ /delete-node/ kernel;
+};
+#endif
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019, Intel Corporation
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_agilex.dtsi"
ethernet2 = &gmac2;
};
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
leds {
compatible = "gpio-leds";
hps0 {
#size-cells = <1>;
qspi_boot: partition@0 {
- label = "Boot and fpga data";
- reg = <0x0 0x034B0000>;
+ label = "u-boot";
+ reg = <0x0 0x04200000>;
};
- qspi_rootfs: partition@34B0000 {
- label = "Root Filesystem - JFFS2";
- reg = <0x034B0000 0x0EB50000>;
+ root: partition@4200000 {
+ label = "root";
+ reg = <0x04200000 0x0BE00000>;
};
};
};