ddr: altera: soc64: Clean up bit-shift by zero bit

Clean up bit-shift by zero bit

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 6783deadc26453c2f6adfcd2f0451c375f5854db..5336ce3991cb21d9993d5b91a587edeb03d3ff01 100644 (file)
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -76,7 +76,7 @@ struct altera_sdram_plat {
 #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK     BIT(16)
 #define DDR_HMC_INTMODE_INTMODE_SET_MSK                BIT(0)
 #define DDR_HMC_RSTHANDSHAKE_MASK              0x0000000f
-#define DDR_HMC_CORE2SEQ_INT_REQ               0xF
+#define DDR_HMC_CORE2SEQ_INT_REQ               0x0000000f
 #define DDR_HMC_SEQ2CORE_INT_RESP_MASK         BIT(3)
 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK                0x001f1f1f
 
@@ -102,90 +102,90 @@ struct altera_sdram_plat {
 #define NIOSRESERVED2                  0x118
 
 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)                        \
-       (((x) >> 0) & 0x1F)
+       ((x) & 0x1f)
 #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)                        \
-       (((x) >> 5) & 0x1F)
+       (((x) >> 5) & 0x1f)
 #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)               \
-       (((x) >> 10) & 0xF)
+       (((x) >> 10) & 0xf)
 #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x)           \
        (((x) >> 14) & 0x3)
 #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x)                 \
        (((x) >> 16) & 0x7)
 
 #define CTRLCFG0_CFG_MEMTYPE(x)                                \
-       (((x) >> 0) & 0xF)
+       ((x) & 0xf)
 #define CTRLCFG0_CFG_DIMM_TYPE(x)                      \
        (((x) >> 4) & 0x7)
 #define CTRLCFG0_CFG_AC_POS(x)                         \
        (((x) >> 7) & 0x3)
 #define CTRLCFG0_CFG_CTRL_BURST_LEN(x)                 \
-       (((x) >> 9) & 0x1F)
+       (((x) >> 9) & 0x1f)
 
 #define CTRLCFG1_CFG_DBC3_BURST_LEN(x)                 \
-       (((x) >> 0) & 0x1F)
+       ((x) & 0x1f)
 #define CTRLCFG1_CFG_ADDR_ORDER(x)                     \
        (((x) >> 5) & 0x3)
 #define CTRLCFG1_CFG_CTRL_EN_ECC(x)                    \
        (((x) >> 7) & 0x1)
 
 #define DRAMTIMING0_CFG_TCL(x)                         \
-       (((x) >> 0) & 0x7F)
+       ((x) & 0x7f)
 
 #define CALTIMING0_CFG_ACT_TO_RDWR(x)                  \
-       (((x) >> 0) & 0x3F)
+       ((x) & 0x3f)
 #define CALTIMING0_CFG_ACT_TO_PCH(x)                   \
-       (((x) >> 6) & 0x3F)
+       (((x) >> 6) & 0x3f)
 #define CALTIMING0_CFG_ACT_TO_ACT(x)                   \
-       (((x) >> 12) & 0x3F)
+       (((x) >> 12) & 0x3f)
 #define CALTIMING0_CFG_ACT_TO_ACT_DB(x)                        \
-       (((x) >> 18) & 0x3F)
+       (((x) >> 18) & 0x3f)
 
 #define CALTIMING1_CFG_RD_TO_RD(x)                     \
-       (((x) >> 0) & 0x3F)
+       ((x) & 0x3f)
 #define CALTIMING1_CFG_RD_TO_RD_DC(x)                  \
-       (((x) >> 6) & 0x3F)
+       (((x) >> 6) & 0x3f)
 #define CALTIMING1_CFG_RD_TO_RD_DB(x)                  \
-       (((x) >> 12) & 0x3F)
+       (((x) >> 12) & 0x3f)
 #define CALTIMING1_CFG_RD_TO_WR(x)                     \
        (((x) >> 18) & 0x3F)
 #define CALTIMING1_CFG_RD_TO_WR_DC(x)                  \
-       (((x) >> 24) & 0x3F)
+       (((x) >> 24) & 0x3f)
 
 #define CALTIMING2_CFG_RD_TO_WR_DB(x)                  \
-       (((x) >> 0) & 0x3F)
+       ((x) & 0x3f)
 #define CALTIMING2_CFG_RD_TO_WR_PCH(x)                 \
-       (((x) >> 6) & 0x3F)
+       (((x) >> 6) & 0x3f)
 #define CALTIMING2_CFG_RD_AP_TO_VALID(x)               \
-       (((x) >> 12) & 0x3F)
+       (((x) >> 12) & 0x3f)
 #define CALTIMING2_CFG_WR_TO_WR(x)                     \
-       (((x) >> 18) & 0x3F)
+       (((x) >> 18) & 0x3f)
 #define CALTIMING2_CFG_WR_TO_WR_DC(x)                  \
-       (((x) >> 24) & 0x3F)
+       (((x) >> 24) & 0x3f)
 
 #define CALTIMING3_CFG_WR_TO_WR_DB(x)                  \
-       (((x) >> 0) & 0x3F)
+       ((x) & 0x3F)
 #define CALTIMING3_CFG_WR_TO_RD(x)                     \
-       (((x) >> 6) & 0x3F)
+       (((x) >> 6) & 0x3f)
 #define CALTIMING3_CFG_WR_TO_RD_DC(x)                  \
-       (((x) >> 12) & 0x3F)
+       (((x) >> 12) & 0x3f)
 #define CALTIMING3_CFG_WR_TO_RD_DB(x)                  \
-       (((x) >> 18) & 0x3F)
+       (((x) >> 18) & 0x3f)
 #define CALTIMING3_CFG_WR_TO_PCH(x)                    \
-       (((x) >> 24) & 0x3F)
+       (((x) >> 24) & 0x3f)
 
 #define CALTIMING4_CFG_WR_AP_TO_VALID(x)               \
-       (((x) >> 0) & 0x3F)
+       ((x) & 0x3f)
 #define CALTIMING4_CFG_PCH_TO_VALID(x)                 \
-       (((x) >> 6) & 0x3F)
+       (((x) >> 6) & 0x3f)
 #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x)             \
-       (((x) >> 12) & 0x3F)
+       (((x) >> 12) & 0x3f)
 #define CALTIMING4_CFG_ARF_TO_VALID(x)                 \
-       (((x) >> 18) & 0xFF)
+       (((x) >> 18) & 0xff)
 #define CALTIMING4_CFG_PDN_TO_VALID(x)                 \
-       (((x) >> 26) & 0x3F)
+       (((x) >> 26) & 0x3f)
 
 #define CALTIMING9_CFG_4_ACT_TO_ACT(x)                 \
-       (((x) >> 0) & 0xFF)
+       ((x) & 0xff)
 
 /* Firewall DDR scheduler MPFE */
 #define FW_HMC_ADAPTOR_REG_ADDR                        0xf8020004