x86: Only align destination to 1x VEC_SIZE in memset 4x loop

Current code aligns to 2x VEC_SIZE. Aligning to 2x has no affect on
performance other than potentially resulting in an additional
iteration of the loop.
1x maintains aligned stores (the only reason to align in this case)
and doesn't incur any unnecessary loop iterations.
Reviewed-by: Sunil K Pandey <skpgkp2@gmail.com>
(cherry picked from commit 9469261cf1924d350feeec64d2c80cafbbdcdd4d)

diff --git a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
index f37be6218a35a2fbe51321e3c97a7540a6b2f850..09fd08ebc0c636c90e2cbd53dd479ee56f409b17 100644 (file)
--- a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
+++ b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
@@ -293,7 +293,7 @@ L(more_2x_vec):
        leaq    (VEC_SIZE * 4)(%rax), %LOOP_REG
 #endif
        /* Align dst for loop.  */
-       andq    $(VEC_SIZE * -2), %LOOP_REG
+       andq    $(VEC_SIZE * -1), %LOOP_REG
        .p2align 4
 L(loop):
        VMOVA   %VMM(0), LOOP_4X_OFFSET(%LOOP_REG)