-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\r
-\r
-#include "mt7621.dtsi"\r
-\r
-#include <dt-bindings/gpio/gpio.h>\r
-#include <dt-bindings/input/input.h>\r
-#include <dt-bindings/leds/common.h>\r
-\r
-/ {\r
- model = "Arcadyan WE410443";\r
- compatible = "arcadyan,we410443", "mediatek,mt7621-soc";\r
-\r
- aliases {\r
- led-boot = &led_status_green;\r
- led-failsafe = &led_status_red;\r
- led-running = &led_status_green;\r
- led-upgrade = &led_status_blue;\r
- };\r
-\r
- keys {\r
- compatible = "gpio-keys";\r
-\r
- wps {\r
- label = "wps";\r
- gpios = <&gpio 3 GPIO_ACTIVE_LOW>;\r
- linux,code = <KEY_WPS_BUTTON>;\r
- };\r
-\r
- reset {\r
- label = "reset";\r
- gpios = <&gpio 18 GPIO_ACTIVE_LOW>;\r
- linux,code = <KEY_RESTART>;\r
- };\r
- };\r
-\r
- leds {\r
- compatible = "gpio-leds";\r
-\r
- led_status_blue: blue {\r
- color = <LED_COLOR_ID_BLUE>;\r
- function = LED_FUNCTION_STATUS;\r
- gpios = <&gpio 41 GPIO_ACTIVE_HIGH>;\r
- };\r
-\r
- led_status_green: green {\r
- color = <LED_COLOR_ID_GREEN>;\r
- function = LED_FUNCTION_STATUS;\r
- gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\r
- };\r
-\r
- led_status_red: red {\r
- color = <LED_COLOR_ID_RED>;\r
- function = LED_FUNCTION_STATUS;\r
- gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\r
- };\r
- };\r
-};\r
-\r
-&spi0 {\r
- status = "okay";\r
-\r
- flash@0 {\r
- compatible = "jedec,spi-nor";\r
- reg = <0>;\r
- spi-max-frequency = <50000000>;\r
-\r
- partitions {\r
- compatible = "fixed-partitions";\r
- #address-cells = <1>;\r
- #size-cells = <1>;\r
-\r
- partition@0 {\r
- label = "all";\r
- reg = <0x0 0x2000000>;\r
- read-only;\r
- };\r
-\r
- partition@1 {\r
- label = "u-boot";\r
- reg = <0x0 0x30000>;\r
- read-only;\r
- };\r
-\r
- partition@30000 {\r
- label = "u-boot-env";\r
- reg = <0x30000 0x10000>;\r
- read-only;\r
- };\r
-\r
- partition@40000 {\r
- label = "factory";\r
- reg = <0x40000 0x10000>;\r
- read-only;\r
-\r
- nvmem-layout {\r
- compatible = "fixed-layout";\r
- #address-cells = <1>;\r
- #size-cells = <1>;\r
-\r
- eeprom_factory_0: eeprom@0 {\r
- reg = <0x0 0x4da8>;\r
- };\r
-\r
- eeprom_factory_8000: eeprom@8000 {\r
- reg = <0x8000 0x4da8>;\r
- };\r
- };\r
- };\r
-\r
- partition@50000 {\r
- compatible = "fixed-partitions";\r
- label = "firmware";\r
- reg = <0x50000 0x1f60000>;\r
- #address-cells = <1>;\r
- #size-cells = <1>;\r
-\r
- partition@0 {\r
- label = "kernel";\r
- reg = <0x0 0x440000>;\r
- };\r
-\r
- partition@400000 {\r
- label = "rootfs";\r
- reg = <0x440000 0x1b20000>;\r
- };\r
- };\r
-\r
- partition@1fb0000 {\r
- label = "glbcfg";\r
- reg = <0x1fb0000 0x10000>;\r
- read-only;\r
- };\r
-\r
- partition@1fc0000 {\r
- label = "config";\r
- reg = <0x1fc0000 0x10000>;\r
- read-only;\r
- };\r
-\r
- partition@1fd0000 {\r
- label = "glbcfg2";\r
- reg = <0x1fd0000 0x10000>;\r
- read-only;\r
- };\r
-\r
- partition@1fe0000 {\r
- label = "config2";\r
- reg = <0x1fe0000 0x10000>;\r
- read-only;\r
- };\r
- };\r
- };\r
-};\r
-\r
-&pcie {\r
- status = "okay";\r
-};\r
-\r
-&pcie0 {\r
- wifi@0,0 {\r
- compatible = "mediatek,mt76";\r
- reg = <0x0000 0 0 0 0>;\r
- nvmem-cells = <&eeprom_factory_0>;\r
- nvmem-cell-names = "eeprom";\r
- ieee80211-freq-limit = <2400000 2500000>;\r
- };\r
-};\r
-\r
-&pcie1 {\r
- wifi@0,0 {\r
- compatible = "mediatek,mt76";\r
- reg = <0x0000 0 0 0 0>;\r
- nvmem-cells = <&eeprom_factory_8000>;\r
- nvmem-cell-names = "eeprom";\r
- ieee80211-freq-limit = <5000000 6000000>;\r
- };\r
-};\r
-\r
-&state_default {\r
- gpio {\r
- groups = "i2c", "wdt", "sdhci";\r
- function = "gpio";\r
- };\r
-};\r
-\r
-&switch0 {\r
- ports {\r
- port@0 {\r
- status = "okay";\r
- label = "lan";\r
- };\r
- };\r
-};\r
-\r
-&xhci {\r
- status = "disabled";\r
-};\r
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Arcadyan WE410443";
+ compatible = "arcadyan,we410443", "mediatek,mt7621-soc";
+
+ aliases {
+ led-boot = &led_status_green;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_blue;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "wps";
+ gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_blue: blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 41 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_green: green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_red: red {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "all";
+ reg = <0x0 0x2000000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "u-boot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+
+ partition@30000 {
+ label = "u-boot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "factory";
+ reg = <0x40000 0x10000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0x4da8>;
+ };
+
+ eeprom_factory_8000: eeprom@8000 {
+ reg = <0x8000 0x4da8>;
+ };
+ };
+ };
+
+ partition@50000 {
+ compatible = "fixed-partitions";
+ label = "firmware";
+ reg = <0x50000 0x1f60000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "kernel";
+ reg = <0x0 0x440000>;
+ };
+
+ partition@400000 {
+ label = "rootfs";
+ reg = <0x440000 0x1b20000>;
+ };
+ };
+
+ partition@1fb0000 {
+ label = "glbcfg";
+ reg = <0x1fb0000 0x10000>;
+ read-only;
+ };
+
+ partition@1fc0000 {
+ label = "config";
+ reg = <0x1fc0000 0x10000>;
+ read-only;
+ };
+
+ partition@1fd0000 {
+ label = "glbcfg2";
+ reg = <0x1fd0000 0x10000>;
+ read-only;
+ };
+
+ partition@1fe0000 {
+ label = "config2";
+ reg = <0x1fe0000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pcie0 {
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom_factory_0>;
+ nvmem-cell-names = "eeprom";
+ ieee80211-freq-limit = <2400000 2500000>;
+ };
+};
+
+&pcie1 {
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom_factory_8000>;
+ nvmem-cell-names = "eeprom";
+ ieee80211-freq-limit = <5000000 6000000>;
+ };
+};
+
+&state_default {
+ gpio {
+ groups = "i2c", "wdt", "sdhci";
+ function = "gpio";
+ };
+};
+
+&switch0 {
+ ports {
+ port@0 {
+ status = "okay";
+ label = "lan";
+ };
+ };
+};
+
+&xhci {
+ status = "disabled";
+};
-From 6688b218552c6fd3178b40d7d106bf732caec3aa Mon Sep 17 00:00:00 2001\r
-From: Mieczyslaw Nalewaj <namiltd@yahoo.com>\r
-Date: Sat, 28 Dec 2024 18:09:17 +0100\r
-Subject: [PATCH] pci-rt2880: static pcibios_init\r
-\r
-Fixes error:\r
-arch/mips/pci/pci-rt2880.c:267:12: error: no previous prototype for 'pcibios_init' [-Werror=missing-prototypes]\r
- 267 | int __init pcibios_init(void)\r
- | ^~~~~~~~~~~~\r
-cc1: all warnings being treated as errors\r
-make[8]: *** [scripts/Makefile.build:229: arch/mips/pci/pci-rt2880.o] Error 1\r
-make[7]: *** [scripts/Makefile.build:478: arch/mips/pci] Error 2\r
-\r
-Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>\r
----\r
- arch/mips/pci/pci-rt2880.c | 7 +++++++\r
- 1 file changed, 7 insertions(+)\r
-\r
+From 6688b218552c6fd3178b40d7d106bf732caec3aa Mon Sep 17 00:00:00 2001
+From: Mieczyslaw Nalewaj <namiltd@yahoo.com>
+Date: Sat, 28 Dec 2024 18:09:17 +0100
+Subject: [PATCH] pci-rt2880: static pcibios_init
+
+Fixes error:
+arch/mips/pci/pci-rt2880.c:267:12: error: no previous prototype for 'pcibios_init' [-Werror=missing-prototypes]
+ 267 | int __init pcibios_init(void)
+ | ^~~~~~~~~~~~
+cc1: all warnings being treated as errors
+make[8]: *** [scripts/Makefile.build:229: arch/mips/pci/pci-rt2880.o] Error 1
+make[7]: *** [scripts/Makefile.build:478: arch/mips/pci] Error 2
+
+Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
+---
+ arch/mips/pci/pci-rt2880.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
--- a/arch/mips/pci/pci-rt2880.c
+++ b/arch/mips/pci/pci-rt2880.c
@@ -264,7 +264,7 @@ static struct platform_driver rt288x_pci
projects / thirdparty / openwrt.git / commitdiff
