From: Jiawei Date: Sun, 11 May 2025 13:38:18 +0000 (+0800) Subject: RISC-V: Add support for RISC-V Profiles 20/22. X-Git-Tag: binutils-2_45~517 X-Git-Url: http://git.ipfire.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=3d7fb9fa5c667c0bf8760dd0db5fee7bb3e05379;p=thirdparty%2Fbinutils-gdb.git RISC-V: Add support for RISC-V Profiles 20/22. This patch introduces support for RISC-V Profiles RV20 and RV22 [1], enabling developers to utilize these profiles through the -march option. [1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0 bfd/ChangeLog: * elfxx-riscv.c (struct riscv_profiles): New struct. (riscv_parse_extensions): New argument. (riscv_find_profiles): New checking function. (riscv_parse_subset): Add Profiles handler. gas/ChangeLog: * NEWS: Add RISC-V Profiles. * doc/as.texi: Update -march input type. * doc/c-riscv.texi: Ditto. * testsuite/gas/riscv/option-arch-fail.l: Modify hint info. * testsuite/gas/riscv/attribute-17.d: New test. * testsuite/gas/riscv/attribute-18.d: New test. * testsuite/gas/riscv/march-fail-rvi20u64v.d: New test. * testsuite/gas/riscv/march-fail-rvi20u64v.l: New test. --- diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index bcb8de49bd3..f4d392413e9 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1022,6 +1022,12 @@ static const struct elf_reloc_map riscv_reloc_map[] = { BFD_RELOC_RISCV_SUB_ULEB128, R_RISCV_SUB_ULEB128 }, }; +struct riscv_profiles +{ + const char *profile_name; + const char *profile_string; +}; + /* Given a BFD reloc type, return a howto structure. */ reloc_howto_type * @@ -1313,6 +1319,31 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {NULL, NULL, NULL} }; +/* This table records the mapping form RISC-V Profiles into march string. */ +static struct riscv_profiles riscv_profiles_table[] = +{ + /* RVI20U only contains the base extension 'i' as mandatory extension. */ + {"rvi20u64", "rv64i"}, + {"rvi20u32", "rv32i"}, + + /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa, + zicclsm,za128rs' as mandatory extensions. */ + {"rva20u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa" + "_zicclsm_za128rs"}, + + /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr, + zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz, + zfhmin,zkt' as mandatory extensions. */ + {"rva22u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt"}, + + /* Currently we do not define S/M mode Profiles. */ + + /* Terminate the list. */ + {NULL, NULL} +}; + /* For default_enable field, decide if the extension should be enbaled by default. */ @@ -1975,10 +2006,11 @@ riscv_parsing_subset_version (const char *p, static const char * riscv_parse_extensions (riscv_parse_subset_t *rps, const char *arch, - const char *p) + const char *p, + bool profile) { - /* First letter must start with i, e or g. */ - if (*p != 'e' && *p != 'i' && *p != 'g') + /* First letter must start with i, e, g or a profile. */ + if (*p != 'e' && *p != 'i' && *p != 'g' && !profile) { rps->error_handler (_("%s: first ISA extension must be `e', `i' or `g'"), @@ -2256,6 +2288,42 @@ riscv_set_default_arch (riscv_parse_subset_t *rps) } } +static bool +riscv_find_profiles (riscv_parse_subset_t *rps, const char **pp) +{ + const char *p = *pp; + + /* Checking if input string contains a Profiles. + There are two cases use Profiles in -march option: + + 1. Only use Profiles in '-march' as input + 2. Mixed Profiles with other extensions + + Use '_' to split Profiles and other extensions. */ + + for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) + { + /* Find profile at the begin. */ + if (startswith (p, riscv_profiles_table[i].profile_name)) + { + /* Handle the profile string. */ + riscv_parse_subset (rps, riscv_profiles_table[i].profile_string); + p += strlen (riscv_profiles_table[i].profile_name); + /* Handle string after profiles if exists. If missing underline + bewteen profile and other extensions, warn the user but not deal + as an error. */ + if (*p != '\0' && *p != '_') + _bfd_error_handler + (_("Warning: should use \"_\" to contact Profiles with other " + "extensions")); + *pp = p; + return true; + } + } + /* Not found profile, return directly. */ + return false; +} + /* Function for parsing ISA string. Return Value: @@ -2293,8 +2361,14 @@ riscv_parse_subset (riscv_parse_subset_t *rps, } } + bool profile = false; p = arch; - if (startswith (p, "rv32")) + if (riscv_find_profiles (rps, &p)) + { + /* Check if using Profiles. */ + profile = true; + } + else if (startswith (p, "rv32")) { *rps->xlen = 32; p += 4; @@ -2315,13 +2389,13 @@ riscv_parse_subset (riscv_parse_subset_t *rps, string is empty. */ if (strlen (arch)) rps->error_handler ( - _("%s: ISA string must begin with rv32 or rv64"), + _("%s: ISA string must begin with rv32, rv64 or Profiles"), arch); return false; } /* Parse single standard and prefixed extensions. */ - if (riscv_parse_extensions (rps, arch, p) == NULL) + if (riscv_parse_extensions (rps, arch, p, profile) == NULL) return false; /* Finally add implicit extensions according to the current diff --git a/gas/NEWS b/gas/NEWS index f28a971736e..6febdc26300 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -8,7 +8,7 @@ to have the same ISA as elf architecture attribute. Once used .option arch directives, the file need to be rebuilt since 2.45. -* Add support for RISC-V privileged version 1.13. +* Add support for RISC-V privileged version 1.13, Profiles. * Add support for RISC-V standard extensions: ssqosid v1.0, ssnpm v1.0, smnpm v1.0, smmpm v1.0, sspm v1.0, supm v1.0, diff --git a/gas/doc/as.texi b/gas/doc/as.texi index 40d45f75d18..6644648ea87 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -552,7 +552,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @emph{Target RISC-V options:} [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}] - [@b{-march}=@var{ISA}] + [@b{-march}=@var{ISA}|@var{Profiles}|@var{Profiles_ISA}] [@b{-mabi}=@var{ABI}] [@b{-mlittle-endian}|@b{-mbig-endian}] @end ifset diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 28ccfb26b4b..a4c819e693a 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -41,9 +41,11 @@ Generate position-independent code @item -fno-pic Don't generate position-independent code (default) -@cindex @samp{-march=ISA} option, RISC-V -@item -march=ISA -Select the base isa, as specified by ISA. For example -march=rv32ima. +@cindex @samp{-march=ISA|Profiles|Profiles_ISA} option, RISC-V +@item -march=ISA|Profiles|Profiles_ISA +Select the base isa, as specified by ISA or Profiles or Profies_ISA. +For example @samp{-march=rv32ima} @samp{-march=RVI20U64} +@samp{-march=RVI20U64_d}. If this option and the architecture attributes aren't set, then assembler will check the default configure setting --with-arch=ISA. @@ -737,7 +739,12 @@ to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands for the default version of its base ISA. On the other hand, the architecture @code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in which the abbreviation @code{G} is expanded to the @code{IMAFD} combination -with default versions of the standard extensions. +with default versions of the standard extensions. All Profiles are expanded + to the mandatory extensions it includes then processing. For example, +@code{RVI20U32} is expanded to @code{RV32I2P0} for processing, which contains +the mandatory extensions @code{I} as it defined. And you can also combine +Profiles with ISA use underline, like @code{RVI20U32_D} is expanded to the +@code{RV32I2P0_F2P0_D2P0}. @item Tag_RISCV_unaligned_access (6) Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned diff --git a/gas/testsuite/gas/riscv/attribute-17.d b/gas/testsuite/gas/riscv/attribute-17.d new file mode 100644 index 00000000000..8e87e8e6995 --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-17.d @@ -0,0 +1,6 @@ +#as: -march=rva20u64 -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0" diff --git a/gas/testsuite/gas/riscv/attribute-18.d b/gas/testsuite/gas/riscv/attribute-18.d new file mode 100644 index 00000000000..2bec0df99a6 --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-18.d @@ -0,0 +1,6 @@ +#as: -march=rvi20u32_d -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0" diff --git a/gas/testsuite/gas/riscv/march-fail-rvi20u64v.d b/gas/testsuite/gas/riscv/march-fail-rvi20u64v.d new file mode 100644 index 00000000000..175db999d6e --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rvi20u64v.d @@ -0,0 +1,3 @@ +#as: -march=rvi20u64v +#source: empty.s +#warning_output: march-fail-rvi20u64v.l diff --git a/gas/testsuite/gas/riscv/march-fail-rvi20u64v.l b/gas/testsuite/gas/riscv/march-fail-rvi20u64v.l new file mode 100644 index 00000000000..ef271798c2c --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rvi20u64v.l @@ -0,0 +1 @@ +.*Warning: should use \"_\" to contact Profiles with other extensions diff --git a/gas/testsuite/gas/riscv/option-arch-fail.l b/gas/testsuite/gas/riscv/option-arch-fail.l index b9979a42618..d83f01d8ad5 100644 --- a/gas/testsuite/gas/riscv/option-arch-fail.l +++ b/gas/testsuite/gas/riscv/option-arch-fail.l @@ -1,5 +1,5 @@ .*Assembler messages: -.*Error: m2p0: ISA string must begin with rv32 or rv64 +.*Error: m2p0: ISA string must begin with rv32, rv64 or Profiles .*Error: cannot \+ or \- base extension `i' in .option arch `\-i' .*Error: cannot \+ or \- base extension `e' in .option arch `\+e' .*Error: cannot \+ or \- base extension `g' in .option arch `\-g'