From: Florian Krohm Date: Fri, 16 May 2025 20:39:42 +0000 (+0000) Subject: s390x: disasm-test: add forgotten opcodes SRNMT, LDE, and LDER X-Git-Url: http://git.ipfire.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=4d0f42954087a4b5320a3364f61172dfdfc9e5b8;p=thirdparty%2Fvalgrind.git s390x: disasm-test: add forgotten opcodes SRNMT, LDE, and LDER --- diff --git a/none/tests/s390x/disasm-test/disasm-test.post.exp b/none/tests/s390x/disasm-test/disasm-test.post.exp index 34722229c..0f31f36ca 100644 --- a/none/tests/s390x/disasm-test/disasm-test.post.exp +++ b/none/tests/s390x/disasm-test/disasm-test.post.exp @@ -1,4 +1,4 @@ -Total: 148751 tests generated -Total: 148659 insns verified +Total: 148776 tests generated +Total: 148684 insns verified Total: 0 disassembly mismatches Total: 92 specification exceptions diff --git a/none/tests/s390x/disasm-test/opcode.c b/none/tests/s390x/disasm-test/opcode.c index ef0649133..e98a5e9e5 100644 --- a/none/tests/s390x/disasm-test/opcode.c +++ b/none/tests/s390x/disasm-test/opcode.c @@ -965,6 +965,7 @@ static const char *opcodes[] = { "pfpo", // pfpo "srnm d12(b2)", "srnmb d12(b2)", // fpext + "srnmt d12(b2)", "sfpc r1", // sfasr not implemented "ste f1,d12(x2,b2)", @@ -976,6 +977,8 @@ static const char *opcodes[] = { // Chapter 10: Control Instructions not implemented // Chapter 14: I/O Instructions not implemented // Chapter 18: Hexadecimal-Floating-Point Instructions not implemented + "lder f1,f2", + "lde f1,d12(x2,b2)", // Chapter 19: Binary-Floating-Point Instructions // Register pairs: 0-2 1-3 4-6 5-7 8-10 9-11 12-14 13-15