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AArch64: Improve codegen in AdvSIMD logs
authorPierre Blanchard <pierre.blanchard@arm.com>
Mon, 9 Dec 2024 15:54:34 +0000 (15:54 +0000)
committerWilco Dijkstra <wilco.dijkstra@arm.com>
Mon, 9 Dec 2024 16:20:34 +0000 (16:20 +0000)
commit8eb5ad2ebc94cc5bedbac57c226c02ec254479c7
tree0298521cce24af837b524c91fce4db97b9a3ffc8tree
parent569cfaaf4984ae70b23c61ee28a609b5aef93feacommit | diff
AArch64: Improve codegen in AdvSIMD logs

Remove spurious ADRP and a few MOVs.
Reduce memory access by using more indexed MLAs in polynomial.
Align notation so that algorithms are easier to compare.
Speedup on Neoverse V1 for log10 (8%), log (8.5%), and log2 (10%).
Update error threshold in AdvSIMD log (now matches SVE log).
sysdeps/aarch64/fpu/log10_advsimd.c diff | blob | blame | history
sysdeps/aarch64/fpu/log2_advsimd.c diff | blob | blame | history
sysdeps/aarch64/fpu/log_advsimd.c diff | blob | blame | history
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