From 41e65df19d4dc3a5f5621ce0e9d74f270d4efb3f Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Thu, 12 Jun 2025 12:26:11 +0100 Subject: [PATCH] [riscv] Maximise barrier effects of memory fences The RISC-V "fence" instruction encoding includes bits for predecessor and successor input and output operations, separate from read and write operations. It is up to the CPU implementation to decide what counts as I/O space rather than memory space for the purposes of this instruction. Since we do not expect fencing to be performance-critical, keep everything as simple and reliable as possible by using the unadorned "fence" instruction (equivalent to "fence iorw, iorw"). Add a memory clobber to ensure that the compiler does not reorder the barrier. (The volatile qualifier seems to already prevent reordering in practice, but this is not guaranteed according to the compiler documentation.) Signed-off-by: Michael Brown --- src/arch/riscv/include/ipxe/riscv_io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/include/ipxe/riscv_io.h b/src/arch/riscv/include/ipxe/riscv_io.h index 8f9030418..be4449ff1 100644 --- a/src/arch/riscv/include/ipxe/riscv_io.h +++ b/src/arch/riscv/include/ipxe/riscv_io.h @@ -128,7 +128,7 @@ RISCV_WRITEX ( w, uint16_t, "h" ); */ static inline __always_inline void IOAPI_INLINE ( riscv, mb ) ( void ) { - __asm__ __volatile__ ( "fence rw, rw" ); + __asm__ __volatile__ ( "fence" : : : "memory" ); } /* Dummy PIO */ -- 2.47.2