clk: clk-axi-clkgen: Add support versal timings

Add proper VCO and PFD limits for versal based platforms. For that we
need to add new Technology and Speed grade defines.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
index fa5ccef73e60ddaaa61b71ddffc2eef099ec401c..26f76a6db82020eb5590dae2f32060042534c9c7 100644 (file)
--- a/drivers/clk/clk-axi-clkgen.c
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -521,7 +521,7 @@ static int axi_clkgen_setup_limits(struct axi_clkgen *axi_clkgen,
                axi_clkgen->limits.fvco_max = 1200000;
                axi_clkgen->limits.fpfd_max = 450000;
                break;
-       case ADI_AXI_FPGA_SPEED_2 ... ADI_AXI_FPGA_SPEED_2LV:
+       case ADI_AXI_FPGA_SPEED_2 ... ADI_AXI_FPGA_SPEED_2MP:
                axi_clkgen->limits.fvco_max = 1440000;
                axi_clkgen->limits.fpfd_max = 500000;
                if (family == ADI_AXI_FPGA_FAMILY_KINTEX || family == ADI_AXI_FPGA_FAMILY_ARTIX) {
@@ -546,6 +546,9 @@ static int axi_clkgen_setup_limits(struct axi_clkgen *axi_clkgen,
        if (tech == ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS) {
                axi_clkgen->limits.fvco_max = 1600000;
                axi_clkgen->limits.fvco_min = 800000;
+       } else if (tech == ADI_AXI_FPGA_TECH_VERSAL) {
+               axi_clkgen->limits.fvco_max = 4320000;
+               axi_clkgen->limits.fvco_min = 2160000;
        }
 
        return 0;

diff --git a/include/linux/adi-axi-common.h b/include/linux/adi-axi-common.h
index 37962ba530dfc1275c17771cade2e75fd7e81cd3..e7ba393061ee6471240b28597d74f8a619de84c4 100644 (file)
--- a/include/linux/adi-axi-common.h
+++ b/include/linux/adi-axi-common.h
@@ -51,6 +51,7 @@ enum adi_axi_fpga_technology {
        ADI_AXI_FPGA_TECH_SERIES7,
        ADI_AXI_FPGA_TECH_ULTRASCALE,
        ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS,
+       ADI_AXI_FPGA_TECH_VERSAL,
 };
 
 enum adi_axi_fpga_family {
@@ -71,6 +72,7 @@ enum adi_axi_fpga_speed_grade {
        ADI_AXI_FPGA_SPEED_2    = 20,
        ADI_AXI_FPGA_SPEED_2L   = 21,
        ADI_AXI_FPGA_SPEED_2LV  = 22,
+       ADI_AXI_FPGA_SPEED_2MP  = 23,
        ADI_AXI_FPGA_SPEED_3    = 30,
 };